Li, Jiang a15a50fc17 [CPU] Enable shared-memory based pipeline parallel for CPU backend (#21289) ...

Signed-off-by: jiang1.li <jiang1.li@intel.com>

2025-07-21 09:07:08 -07:00

..

device_communicators

[CPU] Enable shared-memory based pipeline parallel for CPU backend (#21289)

2025-07-21 09:07:08 -07:00

eplb

Elastic Expert Parallel Initial Support (#20775)

2025-07-18 17:46:09 -07:00

kv_transfer

[BugFix] Make PD work with Ray (#21072)

2025-07-19 08:46:50 -07:00

__init__.py

[Misc] Add SPDX-FileCopyrightText (#19100)

2025-06-03 11:20:17 -07:00

communication_op.py

[Misc] Add SPDX-FileCopyrightText (#19100)

2025-06-03 11:20:17 -07:00

kv_events.py

feat: add data parallel rank to KVEventBatch (#18925)

2025-06-03 17:14:20 -07:00

parallel_state.py

[CPU] Enable shared-memory based pipeline parallel for CPU backend (#21289)

2025-07-21 09:07:08 -07:00

tpu_distributed_utils.py

[Misc] Add SPDX-FileCopyrightText (#20428)

2025-07-04 07:40:42 +00:00

utils.py

[Misc] Add SPDX-FileCopyrightText (#19100)

2025-06-03 11:20:17 -07:00