Cyrus Leung 99267c23ca [2/3] Refactor InternVL-based processors (#37324) ...

Signed-off-by: DarkLight1337 <tlleungac@connect.ust.hk>

2026-03-18 22:22:19 +08:00

..

__init__.py

[CI/Build] Reorganize models tests (#17459)

2025-04-30 23:03:08 -07:00

builders.py

[VLM] Add Qwen3-VL generation test (#25185)

2025-10-29 12:19:37 +00:00

case_filtering.py

[CI/Build] Avoid duplicate empty inputs test for common multimodal generation tests (#29907)

2025-12-03 10:27:36 +00:00

core.py

Fix ExaoneMoeMTP test that never ran in Transformers v4 (#36792)

2026-03-11 17:10:23 +00:00

custom_inputs.py

[ROCm][CI][Bugfix] Fixing the Multi-Modal Models Test (Extended) 1 group (#30013)

2025-12-04 11:00:16 +00:00

model_utils.py

[2/3] Refactor InternVL-based processors (#37324)

2026-03-18 22:22:19 +08:00

runners.py

[VLM] Add Qwen3-VL generation test (#25185)

2025-10-29 12:19:37 +00:00

types.py

[CI/Build] Avoid duplicate empty inputs test for common multimodal generation tests (#29907)

2025-12-03 10:27:36 +00:00