Divakar Verma e6c4797704 [ROCm][Quantization] add fp8xfp8 attn support for rocm_aiter_unified_attn (#36927) ...

Signed-off-by: Divakar Verma <divakar.verma@amd.com>

2026-03-18 08:49:32 +08:00

..

backends

[ROCm][Quantization] add fp8xfp8 attn support for rocm_aiter_unified_attn (#36927)

2026-03-18 08:49:32 +08:00

ops

[Kernel] Add FP8 KV cache support to Triton MLA decode attention (#34597)

2026-03-12 08:32:34 -07:00

__init__.py

[V1] Implement vLLM V1 [1/N] (#9289)

2024-10-22 01:24:07 -07:00

backend.py

[Misc] Add float16 to CacheDType (#37199)

2026-03-16 13:24:48 -07:00

selector.py

Reapply [Attention] Refactor check_and_update_config (#35122)

2026-03-09 07:17:14 -07:00