Flora Feng 53415653ff [P/D][Nixl] Make kv cache register compatible with hybrid memory allocator (#23079) ...

Signed-off-by: sfeng33 <4florafeng@gmail.com>

2025-08-21 22:30:48 -07:00

..

__init__.py

[P/D] NIXL Integration (#17751)

2025-05-12 09:46:16 -07:00

test_multi_connector.py

[Attention] MLA - Flashinfer Ragged Prefill (#20034)

2025-07-10 20:17:47 -07:00

test_nixl_connector.py

[P/D][Nixl] Make kv cache register compatible with hybrid memory allocator (#23079)

2025-08-21 22:30:48 -07:00

test_output_aggreagator.py

[V1] [P/D] Refactor KV Connector Path (#21980)

2025-08-03 04:03:40 -07:00

test_remote_decode_lifecycle.py

[v1] Move block_hashes from KVCacheManager to Request.block_hashes (#19728)

2025-08-15 16:52:52 -07:00

test_remote_prefill_lifecycle.py

[v1] Move block_hashes from KVCacheManager to Request.block_hashes (#19728)

2025-08-15 16:52:52 -07:00

test_shared_storage_connector.py

[CI Bugfix] Fix wNa16 kernel not found for test_shared_storage_connector_hashes (#22163)

2025-08-03 22:19:04 -07:00

utils.py

[Spec Decode] Make propose_draft_token_ids non-blocking for lower TTFT (#23041)

2025-08-18 17:20:38 -07:00