Li, Jiang a2ae496589 [CPU] Support FP8 KV cache (#14741) ...

Signed-off-by: jiang1.li <jiang1.li@intel.com>

2025-03-14 22:07:36 -07:00

..

backends

[CPU] Support FP8 KV cache (#14741)

2025-03-14 22:07:36 -07:00

ops

[Kernel] [V1] Further optimizations to ROCm (Triton) Backend to better handle GQA. (#14431)

2025-03-13 20:42:27 -07:00

__init__.py

[Attention] MLA with chunked prefill (#12639)

2025-02-21 15:30:12 -08:00

layer.py

[Bug] Fix Attention when ignored in by quant_method (#14313)

2025-03-06 14:18:06 -08:00

selector.py

Correct capitalisation: VLLM -> vLLM (#14562)

2025-03-10 16:36:21 +00:00