Anton Ivanov
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abebd9323d
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[CPU] Replace OMP initialization (#36487)
Signed-off-by: Anton Ivanov <anton.ivanov@cambridgegreys.com>
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2026-04-03 18:42:43 +08:00 |
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Li, Jiang
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352b90c4a4
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[Bugfix] Add replacement of _compute_slot_mapping_kernel on CPU (#37987)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-03-24 07:00:20 -07:00 |
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yassha
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199f914183
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fix(cpu): add null check for aligned_alloc in ScratchPadManager (#37369)
Signed-off-by: yassha <50112520+yassha@users.noreply.github.com>
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2026-03-19 17:45:06 +08:00 |
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skaraban3807
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7cd288a4b3
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[PERF] Add interleaved memory allocation to NUMA module (#30800)
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2025-12-24 13:47:49 +00:00 |
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Li, Jiang
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f90d3636e2
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[Bugfix][CPU] Fix Mac CPU build (#30955)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-12-18 01:38:22 -08:00 |
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Li, Jiang
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e3ab93c896
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[CPU] Refactor CPU fused MOE (#30531)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-12-18 14:36:49 +08:00 |
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Li, Jiang
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e2f56c309d
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[CPU] Update torch 2.9.1 for CPU backend (#29664)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-11-28 13:37:54 +00:00 |
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skaraban3807
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f1805db1a6
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[Perf] These changes enhance the NUMA functionality of vllm for systems with more than one NUMA nodes per socket (#25559)
Signed-off-by: Siddappa Karabannavar <siddappa.karabannavar@amd.com>
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2025-11-21 14:13:52 +00:00 |
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usberkeley
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4ab34f6ef1
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Add NUMA node validation for CPU thread binding (#28555)
Signed-off-by: Bradley <bradley.b.pitt@gmail.com>
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2025-11-13 07:03:52 +00:00 |
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Louie Tsai
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5c8d34a42c
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Support no privileged mode on CPU for docker and kubernetes deployments (#19241)
Signed-off-by: Tsai, Louie <louie.tsai@intel.com>
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2025-06-11 04:11:47 -07:00 |
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rongfu.leng
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4e9cf8c1dd
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[Bugfix] fix gettid method is not define (#16084)
Signed-off-by: rongfu.leng <rongfu.leng@daocloud.io>
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2025-04-08 19:12:44 -07:00 |
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Li, Jiang
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550b2801ad
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[CPU][Bugfix] Using custom allreduce for CPU backend (#15934)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-04-02 07:46:47 -07:00 |
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Wallas Henrique
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cfd3219f58
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[Hardware][Apple] Native support for macOS Apple Silicon (#11696)
Signed-off-by: Wallas Santos <wallashss@ibm.com>
Co-authored-by: Michael Goin <michael@neuralmagic.com>
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2025-01-08 16:35:49 +08:00 |
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Li, Jiang
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0b952af458
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[Hardware][Intel] Support compressed-tensor W8A8 for CPU backend (#7257)
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2024-09-11 09:46:46 -07:00 |
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Li, Jiang
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3bbb4936dc
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[Hardware] [Intel] Enable Multiprocessing and tensor parallel in CPU backend and update documentation (#6125)
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2024-07-26 13:50:10 -07:00 |
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