From f5d7049cc119e9bc572f29267e270b82a39d6ec1 Mon Sep 17 00:00:00 2001 From: linhaifeng <1371675203@qq.com> Date: Wed, 28 Jan 2026 04:33:29 +0800 Subject: [PATCH] [Bugfix] Fix display error (inconsistent with context) (#33020) Signed-off-by: linhaifeng <1371675203@qq.com> --- vllm/engine/arg_utils.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vllm/engine/arg_utils.py b/vllm/engine/arg_utils.py index 16e3dcc67..82be97ce6 100644 --- a/vllm/engine/arg_utils.py +++ b/vllm/engine/arg_utils.py @@ -1951,13 +1951,13 @@ class EngineArgs: CpuArchEnum.RISCV, ): logger.info( - "Chunked prefill is not supported for ARM and POWER, " + "Chunked prefill is not supported for POWER, " "S390X and RISC-V CPUs; " "disabling it for V1 backend." ) self.enable_chunked_prefill = False logger.info( - "Prefix caching is not supported for ARM and POWER, " + "Prefix caching is not supported for POWER, " "S390X and RISC-V CPUs; " "disabling it for V1 backend." )