From e03ddcfbd4d686c91f6509c5451546437bbbf3e5 Mon Sep 17 00:00:00 2001 From: Akash kaothalkar <61960177+Akashcodes732@users.noreply.github.com> Date: Thu, 26 Feb 2026 15:51:24 +0530 Subject: [PATCH] [Hardware][Powerpc]Enable prefix caching and chunked prefill for ppc64le (#35081) Signed-off-by: Akash kaothalkar Co-authored-by: Akash kaothalkar --- vllm/engine/arg_utils.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/vllm/engine/arg_utils.py b/vllm/engine/arg_utils.py index 036178887..2e9cd6634 100644 --- a/vllm/engine/arg_utils.py +++ b/vllm/engine/arg_utils.py @@ -2076,20 +2076,19 @@ class EngineArgs: ) # Disable chunked prefill and prefix caching for: - # POWER (ppc64le)/RISCV CPUs in V1 + # RISCV CPUs in V1 if current_platform.is_cpu() and current_platform.get_cpu_architecture() in ( - CpuArchEnum.POWERPC, CpuArchEnum.RISCV, ): logger.info( - "Chunked prefill is not supported for POWER, " - "and RISC-V CPUs; " + "Chunked prefill is not supported for" + "RISC-V CPUs; " "disabling it for V1 backend." ) self.enable_chunked_prefill = False logger.info( - "Prefix caching is not supported for POWER, " - "and RISC-V CPUs; " + "Prefix caching is not supported for " + "RISC-V CPUs; " "disabling it for V1 backend." ) self.enable_prefix_caching = False