[CI] execute all piecewise compilation tests together (#24502)
Signed-off-by: zjy0516 <riverclouds.zhu@qq.com>
This commit is contained in:
@@ -4,9 +4,9 @@
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Test (piecewise) compilation with a simple model where multiple submodules
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are compiled and graph captured separately.
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"""
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import torch
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from torch import nn
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from torch.library import Library
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from vllm.compilation.backends import set_model_tag
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from vllm.compilation.counter import compilation_counter
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@@ -15,10 +15,9 @@ from vllm.compilation.decorators import (ignore_torch_compile,
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from vllm.config import (CompilationConfig, CompilationLevel, CUDAGraphMode,
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VllmConfig, set_current_vllm_config)
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from vllm.forward_context import BatchDescriptor, set_forward_context
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from vllm.utils import direct_register_custom_op
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# create a library to hold the custom op
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silly_lib = Library("silly", "FRAGMENT") # noqa
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# This import automatically registers `torch.ops.silly.attention`
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from .. import silly_attention # noqa: F401
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BATCH_SIZE = 32
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MLP_SIZE = 128
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@@ -26,27 +25,6 @@ HIDDEN_SIZE = 1024
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RANDOM_SEED = 0
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def silly_attention(q: torch.Tensor, k: torch.Tensor, v: torch.Tensor,
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out: torch.Tensor) -> None:
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out.copy_(q)
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out += k
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out += v
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def silly_attention_fake(q: torch.Tensor, k: torch.Tensor, v: torch.Tensor,
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out: torch.Tensor) -> None:
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return
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direct_register_custom_op(
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op_name="attention",
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op_func=silly_attention,
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mutates_args=["out"],
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fake_impl=silly_attention_fake,
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target_lib=silly_lib,
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)
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@support_torch_compile
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class ParentModel(nn.Module):
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