biondizzle fa2d5708c5 debug: add L1 GEMM and SiLU output debug prints

2026-05-16 19:29:42 +00:00

..

kernel

refactor: copy CuTeDSL kernel into repo with local imports

2026-05-16 02:57:54 +00:00

__init__.py

refactor: copy CuTeDSL kernel into repo with local imports

2026-05-16 02:57:54 +00:00

bridge.py

fix: L1 weight N dimension is 2*intermediate (gate+up), not intermediate

2026-05-16 19:07:08 +00:00

moe_pipeline.py

debug: add L1 GEMM and SiLU output debug prints

2026-05-16 19:29:42 +00:00