186 lines
6.8 KiB
Python
186 lines
6.8 KiB
Python
"""
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SMEM-P Coordinate Verification Test.
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Writes a known pattern to sP using the coordinate-indexed approach
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(identical to FmhaKernel's SMEM-P path), then reads sP back
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via a simple SMEM→GMEM copy and verifies on the host.
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Pattern: sP[m, k] = float(m*128 + k) (unique value per position)
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Expected: output[m, k] = float(m*128 + k) after round-trip
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If coordinates are correct, all values match.
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If coordinates are wrong, values will be at different positions.
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"""
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import torch, math
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import cutlass, cutlass.cute as cute
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import cutlass.utils as utils
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from cutlass.cute.nvgpu import tcgen05
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from cutlass import Float32, BFloat16, Int32, const_expr
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from cutlass.utils import LayoutEnum
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import cutlass.torch as ct
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import cuda.bindings.driver as cuda
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import cutlass.pipeline as pipeline
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@cute.jit
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def smem_p_coord_test(
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mOut, qk_mma, pv_mma, qk_mma_tiler, pv_mma_tiler, p_smem_s
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):
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"""Write known pattern to sP using coordinate-indexed approach, read back."""
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tidx, _, _ = cute.arch.thread_idx()
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warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())
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# 5 warps: 4 softmax + 1 for TMEM alloc
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if warp_idx >= 5:
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return
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# SMEM allocation
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smem = utils.SmemAllocator()
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tmem_bar = pipeline.NamedBarrier(barrier_id=2, num_threads=32 * 5)
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sP = smem.allocate_tensor(element_type=BFloat16, layout=p_smem_s.outer, byte_alignment=128, swizzle=p_smem_s.inner)
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sP_nostage = sP[(None, None, None, 0)]
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# TMEM allocation
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tmem = utils.TmemAllocator(None, barrier_for_retrieve=tmem_bar, allocator_warp_id=4, is_two_cta=False)
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if warp_idx == 4:
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tmem.allocate(128)
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tmem.wait_for_alloc()
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tmem_ptr = tmem.retrieve_ptr(Float32)
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# QK C-fragment (for TMEM layout)
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qk_thr = qk_mma.get_slice(0)
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qk_as = qk_thr.partition_shape_C(qk_mma_tiler[:2])
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tStS = qk_thr.make_fragment_C(qk_as)
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tStS0 = cute.make_tensor(tStS.iterator, tStS.layout)
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# TMEM-load copy (same as FmhaKernel)
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tmem_load_atom = cute.make_copy_atom(tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)), Float32)
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tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tStS0)
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# Softmax warps: write known pattern to sP
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if warp_idx < 4:
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sfw_idx = tidx % 128 # 4 softmax warps
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thr_load = tiled_tmem_load.get_slice(sfw_idx)
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# Coordinate identity tensor
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cS = cute.make_identity_tensor((128, 128))
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tScS = qk_thr.partition_C(cS)
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tTMEM_LOADcS = thr_load.partition_D(tScS)
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# Write known pattern to sP using coordinate-indexed approach
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for j0 in range(32):
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for j1 in range(4):
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coord = tTMEM_LOADcS[(j0, 0), j1, 0, 0]
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m_coord = coord[0]
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k_coord = coord[1]
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k0 = k_coord % 16
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k1 = (k_coord // 16) % 4
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k2 = k_coord // 64
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# Pattern: value = (m * 128 + k) as BF16
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val = BFloat16(m_coord * 128 + k_coord)
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sP_nostage[(m_coord, k0), 0, (k1, k2)] = val
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cute.arch.fence_proxy("async.shared", space="cta")
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# Barrier between softmax writes and read-back
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sync_bar = pipeline.NamedBarrier(barrier_id=3, num_threads=32 * 5)
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sync_bar.arrive_and_wait()
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# Read sP back to global memory
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# Thread 0 of warp 0 does the read (simple sequential access)
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if tidx == 0:
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gOut = mOut # (128, 128) output
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for m in range(128):
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for k in range(128):
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k0 = k % 16
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k1 = (k // 16) % 4
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k2 = k // 64
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val = sP_nostage[(m, k0), 0, (k1, k2)]
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gOut[m, k] = val
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if warp_idx < 4:
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tmem.relinquish_alloc_permit()
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tmem.free(tmem_ptr)
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def main():
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head_dim = 256
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s_k = 128
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m = 128
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pv_n_tile = min(head_dim, 256)
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# Create tensors for layout derivation
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q = torch.randn(m, head_dim, 1, dtype=torch.bfloat16, device='cuda')
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k = torch.randn(s_k, head_dim, 1, dtype=torch.bfloat16, device='cuda')
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v = torch.randn(s_k, head_dim, dtype=torch.bfloat16, device='cuda')
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mQ = ct.from_dlpack(q).mark_layout_dynamic(leading_dim=ct.get_leading_dim(q))
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mK = ct.from_dlpack(k).mark_layout_dynamic(leading_dim=ct.get_leading_dim(k))
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v_tile = v[:, 0:pv_n_tile].contiguous().unsqueeze(-1)
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mV = ct.from_dlpack(v_tile).mark_layout_dynamic(leading_dim=ct.get_leading_dim(v_tile))
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a_major = LayoutEnum.from_tensor(mQ).mma_major_mode()
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b_major = LayoutEnum.from_tensor(mK).mma_major_mode()
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v_major = LayoutEnum.from_tensor(mV).mma_major_mode()
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qk_mma = utils.sm100.make_trivial_tiled_mma(
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BFloat16, BFloat16, a_major, b_major, Float32,
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tcgen05.CtaGroup.ONE, (128, 128), tcgen05.OperandSource.SMEM
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)
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pv_mma = utils.sm100.make_trivial_tiled_mma(
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BFloat16, BFloat16, a_major, v_major, Float32,
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tcgen05.CtaGroup.ONE, (128, pv_n_tile), tcgen05.OperandSource.SMEM
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)
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qk_ik = cute.size(qk_mma.shape_mnk, mode=[2])
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qk_mma_tiler = (128, 128, qk_ik * 4)
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pv_ik = cute.size(pv_mma.shape_mnk, mode=[2])
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pv_mma_tiler = (128, pv_n_tile, pv_ik * (128 // pv_ik))
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p_smem_s = utils.sm100.make_smem_layout_a(pv_mma, pv_mma_tiler, BFloat16, 1)
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# Output tensor
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out = torch.zeros(128, 128, dtype=torch.bfloat16, device='cuda')
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mOut = ct.from_dlpack(out).mark_layout_dynamic(leading_dim=ct.get_leading_dim(out))
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stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)
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print("Compiling...")
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compiled = cute.compile(smem_p_coord_test, mOut, qk_mma, pv_mma, qk_mma_tiler, pv_mma_tiler, p_smem_s)
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print("Running...")
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compiled(mOut, qk_mma, pv_mma, qk_mma_tiler, pv_mma_tiler, p_smem_s, stream)
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torch.cuda.synchronize()
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# Verify: out[m, k] should be m*128 + k
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out_float = out.float()
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expected = torch.arange(128, dtype=torch.float32, device='cuda').unsqueeze(0) * 128 + torch.arange(128, dtype=torch.float32, device='cuda').unsqueeze(1)
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# Check a few values
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print(f"\n=== Verification ===")
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n_correct = 0
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n_total = 128 * 128
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for m in range(128):
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for k in range(128):
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exp = float(m * 128 + k)
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got = out_float[m, k].item()
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if abs(got - exp) < 1.0: # BF16 precision
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n_correct += 1
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elif n_correct > 0 and n_correct < 5:
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print(f" MISMATCH at ({m},{k}): expected {exp}, got {got}")
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accuracy = n_correct / n_total * 100
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print(f" Accuracy: {n_correct}/{n_total} = {accuracy:.1f}%")
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# Print a few sample values
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print(f"\n Sample values:")
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for m in [0, 1, 2, 64, 127]:
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for k in [0, 1, 16, 32, 64, 127]:
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exp = float(m * 128 + k)
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got = out_float[m, k].item()
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status = "✓" if abs(got - exp) < 1.0 else "✗"
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print(f" [{m},{k}] expected={exp:.0f} got={got:.1f} {status}")
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if __name__ == '__main__':
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main()
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