317 lines
15 KiB
Python
317 lines
15 KiB
Python
"""
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D1.3 SMEM-P: Diagnostic for make_cotiled_copy approach.
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Runs a minimal kernel that:
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1. Prints tiled_tmem_load TV layout shapes
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2. Prints tTMEM_LOADcS coordinate partition shapes
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3. Prints sP layout shapes
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4. Attempts to build make_cotiled_copy and prints partition shapes
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"""
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import torch, math
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import cutlass, cutlass.cute as cute, cutlass.utils as utils
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from cutlass.cute.nvgpu import cpasync, tcgen05
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from cutlass import Float32, BFloat16, Int32, const_expr
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from cutlass.utils import LayoutEnum
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from cutlass.utils.tmem_allocator import find_tmem_tensor_col_offset
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import cutlass.torch as ct
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import cuda.bindings.driver as cuda
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class SmemPDiag:
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def __init__(self, head_dim=64, s_k=128):
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self.head_dim = head_dim
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self.s_k = s_k
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self.pv_n_tile = min(head_dim, 256)
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self.use_smem_p = True # We're diagnosing SMEM-P
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self.normalize = False
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self.qk_mma_tiler = (128, 128, 128 * 4)
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self.pv_mma_tiler = (128, self.pv_n_tile, 128)
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self.acc_dtype = Float32
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self.qk_acc_dtype = Float32
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self.q_dtype = BFloat16
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self.o_dtype = BFloat16
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self.use_2cta_instrs = False
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self.cta_group = tcgen05.CtaGroup.ONE
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self.cluster_shape_mn = (1, 1)
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self.epilogue_warp_id = (0, 1, 2, 3)
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self.mma_warp_id = 4
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self.tma_warp_id = 5
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self.threads_per_cta = 192
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self.num_acc_stage = 1
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self.scale_softmax_log2 = 1.0 / math.sqrt(self.head_dim) * math.log2(math.e)
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self.kv_stage = 2
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self.q_stage = 1
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self.num_c_stage = 2
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self.c_layout = LayoutEnum.ROW_MAJOR
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@cute.jit
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def __call__(self, q, k, v, c, stream):
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self.a_major = LayoutEnum.from_tensor(q).mma_major_mode()
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self.b_major = LayoutEnum.from_tensor(k).mma_major_mode()
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v_fmha = cute.make_tensor(
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v.iterator,
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cute.make_layout(
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(self.pv_n_tile, self.s_k, 1),
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stride=(1, self.pv_n_tile, self.pv_n_tile * self.s_k),
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),
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)
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self.v_major = LayoutEnum.from_tensor(v_fmha).mma_major_mode()
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qk_mma = utils.sm100.make_trivial_tiled_mma(
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self.q_dtype, self.q_dtype, self.a_major, self.b_major,
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self.qk_acc_dtype, self.cta_group, (128, 128), tcgen05.OperandSource.SMEM
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)
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pv_a_major = cute.nvgpu.OperandMajorMode.K # SMEM-P uses K major
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pv_mma = utils.sm100.make_trivial_tiled_mma(
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self.q_dtype, self.q_dtype, pv_a_major, self.v_major,
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self.qk_acc_dtype, self.cta_group, (128, self.pv_n_tile),
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tcgen05.OperandSource.SMEM
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)
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# Setup TMEM offsets (simplified for SMEM-P)
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qk_thr = qk_mma.get_slice(0)
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qk_as = qk_thr.partition_shape_C(self.qk_mma_tiler[:2])
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tStS = qk_thr.make_fragment_C(qk_as)
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pv_thr = pv_mma.get_slice(0)
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pv_as = pv_thr.partition_shape_C(self.pv_mma_tiler[:2])
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tOtO = pv_thr.make_fragment_C(pv_as)
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self.tmem_s0_offset = 0
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self.tmem_p0_offset = -1 # SMEM-P
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self.tmem_o0_offset = 0
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s_cols = self.qk_mma_tiler[1]
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o_cols = find_tmem_tensor_col_offset(tOtO)
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total = max(s_cols, o_cols)
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_n = 1
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while _n < total:
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_n *= 2
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self.num_tmem_alloc_cols = _n
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self.tOrP0_offset = 0 # SMEM-P
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# Build SMEM layouts
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p_smem_s = utils.sm100.make_smem_layout_a(pv_mma, self.pv_mma_tiler, self.q_dtype, 1)
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q_smem_s = utils.sm100.make_smem_layout_a(qk_mma, self.qk_mma_tiler, self.q_dtype, self.q_stage)
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k_smem_s = utils.sm100.make_smem_layout_b(qk_mma, self.qk_mma_tiler, self.q_dtype, self.kv_stage)
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v_smem_s = utils.sm100.make_smem_layout_b(pv_mma, self.pv_mma_tiler, self.q_dtype, self.kv_stage)
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c_smem_s = utils.sm100.make_smem_layout_epi(self.o_dtype, self.c_layout, (128, self.pv_n_tile), 2)
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# TMA atoms
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q_s = cute.slice_(q_smem_s, (None, None, None, 0))
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k_s = cute.slice_(k_smem_s, (None, None, None, 0))
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v_s = cute.slice_(v_smem_s, (None, None, None, 0))
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cta = cute.size(qk_mma.thr_id.shape)
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self.q_tx_bytes = cute.size_in_bytes(self.q_dtype, q_s) * cta
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self.kv_tx_bytes = (cute.size_in_bytes(self.q_dtype, k_s) + cute.size_in_bytes(self.q_dtype, v_s)) * cta
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tma_q, mQ = cute.nvgpu.make_tiled_tma_atom_A(
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utils.sm100.cluster_shape_to_tma_atom_A(self.cluster_shape_mn, qk_mma.thr_id),
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q, q_s, self.qk_mma_tiler, qk_mma, (1, 1, 1, 1)
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)
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tma_k, mK = cute.nvgpu.make_tiled_tma_atom_B(
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utils.sm100.cluster_shape_to_tma_atom_B(self.cluster_shape_mn, qk_mma.thr_id),
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k, k_s, self.qk_mma_tiler, qk_mma, (1, 1, 1, 1)
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)
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tma_v, mV = cute.nvgpu.make_tiled_tma_atom_B(
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utils.sm100.cluster_shape_to_tma_atom_B(self.cluster_shape_mn, pv_mma.thr_id),
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v_fmha, v_s, self.pv_mma_tiler, pv_mma, (1, 1, 1, 1)
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)
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epi_s = cute.select(c_smem_s, mode=[0, 1])
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tma_c, mC = cpasync.make_tiled_tma_atom(cpasync.CopyBulkTensorTileS2GOp(), c, epi_s, (128, self.pv_n_tile))
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# ===== KERNEL =====
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self._kernel(qk_mma, pv_mma, tma_q, mQ, tma_k, mK, tma_v, mV, tma_c, mC,
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p_smem_s, q_smem_s, k_smem_s, v_smem_s, c_smem_s,
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tStS, tOtO, qk_thr, pv_thr).launch(
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grid=(1, 1, 1), block=[self.threads_per_cta, 1, 1], stream=stream
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)
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@cute.kernel
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def _kernel(self, qk_mma, pv_mma, tma_q, mQ, tma_k, mK, tma_v, mV, tma_c, mC,
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p_smem_s, q_smem_s, k_smem_s, v_smem_s, c_smem_s,
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tStS, tOtO, qk_thr, pv_thr):
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tidx, _, _ = cute.arch.thread_idx()
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warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())
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@cute.struct
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class SS:
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q_bar: cute.struct.MemRange[cutlass.Int64, self.q_stage * 2]
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kv_bar: cute.struct.MemRange[cutlass.Int64, self.kv_stage * 2]
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s_bar: cute.struct.MemRange[cutlass.Int64, 2]
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acc_bar: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage * 2]
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tmem_dealloc: cutlass.Int64
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holding: cutlass.Int32
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smem = utils.SmemAllocator()
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st = smem.allocate(SS)
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sQ = smem.allocate_tensor(element_type=self.q_dtype, layout=q_smem_s.outer, byte_alignment=128, swizzle=q_smem_s.inner)
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sK = smem.allocate_tensor(element_type=self.q_dtype, layout=k_smem_s.outer, byte_alignment=128, swizzle=k_smem_s.inner)
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sV = smem.allocate_tensor(element_type=self.q_dtype, layout=v_smem_s.outer, byte_alignment=128, swizzle=v_smem_s.inner)
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sP = smem.allocate_tensor(element_type=self.q_dtype, layout=p_smem_s.outer, byte_alignment=128, swizzle=p_smem_s.inner)
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# ===== PRINT DIAGNOSTICS (only from warp 0, thread 0) =====
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if warp_idx < 4: # softmax warps
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# TMEM load atoms
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tmem_load_atom = cute.make_copy_atom(tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)), self.qk_acc_dtype)
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tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tStS)
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sfw_idx = tidx % (32 * len(self.epilogue_warp_id))
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thr_load = tiled_tmem_load.get_slice(sfw_idx)
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tTMEM_LOADtS = thr_load.partition_S(tStS)
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cS = cute.make_identity_tensor((self.qk_mma_tiler[0], self.qk_mma_tiler[1]))
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tScS = qk_thr.partition_C(cS)
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tTMEM_LOADcS = thr_load.partition_D(tScS)
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if sfw_idx == 0:
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print(f"=== TMEM Load Diagnostics (sfw_idx=0) ===")
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print(f"tiled_tmem_load shape: {cute.shape(tiled_tmem_load)}")
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print(f"tTMEM_LOADtS shape: {cute.shape(tTMEM_LOADtS)}")
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print(f"tTMEM_LOADtS layout: {tTMEM_LOADtS.layout}")
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print(f"tTMEM_LOADcS shape: {cute.shape(tTMEM_LOADcS)}")
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print(f"tTMEM_LOADcS layout: {tTMEM_LOADcS.layout}")
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# Print TV layout
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tv = tiled_tmem_load.layout_dst_tv_tiled
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print(f"TV layout: {tv}")
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print(f"TV layout shape: {cute.shape(tv)}")
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# Print sP layout
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sP_stage = sP[(None, None, None, 0)]
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print(f"sP shape: {cute.shape(sP)}")
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print(f"sP layout (outer): {sP.layout}")
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print(f"sP_stage shape: {cute.shape(sP_stage)}")
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print(f"sP_stage layout: {sP_stage.layout}")
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# Print tStS layout
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print(f"tStS shape: {cute.shape(tStS)}")
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print(f"tStS layout: {tStS.layout}")
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# Try to build make_cotiled_copy
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# atom_layout_tv: (tid, vid) -> sP flat address
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# We need to map from the TV layout's codomain (tStS addresses)
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# to sP addresses.
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#
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# tStS layout: ((128,128),1,1):((65536,1),0,0)
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# So tStS_addr(m,k) = m*65536 + k
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# sP layout: ((128,16),1,(4,2),1):(((64,1),0,((16,8192),0)
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# So sP_addr((m,k0),0,(k1,k2),0) = m*64 + k0 + k1*16 + k2*8192
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# where k0=k%16, k1=(k//16)%4, k2=k//64
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#
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# We can't directly compose because the codomains are different.
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# But we CAN build a new Layout that maps (tid, vid) -> sP addr.
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#
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# The key: enumerate all (tid, vid) pairs, find their (m, k) from
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# tTMEM_LOADcS, then compute sP_addr.
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# But we can't do this at Python trace time inside @cute.kernel
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# because we don't have the actual coordinate values.
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#
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# OR: we can try composition. Let's see if
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# cute.composition(sP_stage.layout, tv) works.
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# This requires the codomain of tv to be compatible with
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# the domain of sP_stage.layout.
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print(f"\n=== Attempting composition ===")
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print(f"TV codomain size: {cute.size(tv)}")
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print(f"sP_stage domain size: {cute.size(sP_stage.layout)}")
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# Try: make a layout that maps (m, k) -> sP_addr
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# then compose with the inverse of tStS.layout
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# Actually, tStS has 3 modes. Let me flatten it.
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# The 2D logical P is (128, 128) = (M, K)
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# tStS has layout ((128,128),1,1):((65536,1),0,0)
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# The 2D part is (128,128) with strides (65536, 1)
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# So the 2D layout is: (128, 128) : (65536, 1)
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# sP_stage has shape ((128,16),1,(4,2),1)
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# The logical P is 128 x 128 where:
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# mode0: (128, 16) with strides (64, 1)
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# mode2: (4, 2) with strides (16, 8192)
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# So the 2D logical layout (grouping modes 0 and 2) is:
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# (128*4, 16*2) = (512, 32) with... complex strides.
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# Actually, sP is 4D, not 2D.
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# Let me try the group_modes approach:
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sP_2d = cute.group_modes(sP_stage, 0, 4) # flatten to 1D? No.
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# group_modes(sP, 0, 4) makes it (N,) where N = total elements
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# Actually group_modes(sP, 0, 4) groups the first 4 modes into 1
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# and keeps the rest. sP_stage has 4 modes -> becomes 1 mode.
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# That's just a 1D tensor.
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print(f"sP_2d (grouped) shape: {cute.shape(sP_2d)}")
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print(f"sP_2d layout: {sP_2d.layout}")
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# Now try to compose the TV layout with the identity tensor's layout
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# to get (tid, vid) -> (m, k), then use that to index into sP.
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# Actually, the right approach per the CUTLASS LLM:
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# 1. Build a custom atom_layout_tv from scratch
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# 2. Each thread's (m, k) pairs come from tTMEM_LOADcS
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# 3. Convert (m, k) to sP address
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# 4. Build a Layout((n_threads, n_vals_per_thread), (sP_addr_strides,))
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#
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# But building this at trace time requires knowing all (m, k) values.
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# The identity tensor partition tTMEM_LOADcS has these values
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# but they're runtime values in CuTeDSL, not Python values.
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#
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# HOWEVER: since tTMEM_LOADcS is an identity tensor partition,
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# the coordinates are STATIC (known at compile/trace time).
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# We should be able to extract them at Python trace time.
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#
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# Let me check: can we iterate over tTMEM_LOADcS at trace time?
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# tTMEM_LOADcS has shape ((32,1),4,1,1)
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# Each element is a (m, k) pair.
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# At trace time, cute.shape gives us the static shape.
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# But the actual coordinate VALUES might be dynamic.
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#
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# In CuTe, identity tensors have static values.
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# cute.make_identity_tensor((M, K)) creates a tensor where
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# the value at each coordinate IS the coordinate.
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# So tTMEM_LOADcS[j0, j1, 0, 0] should give a static (m, k) pair.
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# At trace time, we should be able to extract these.
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#
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# But wait - at trace time, the identity tensor is being traced.
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# The values are MLIR constants, not Python ints.
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# We can't iterate and build a Python Layout from them.
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#
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# The alternative: define atom_layout_tv analytically.
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# The Ld32x32bOp with Repetition(32) partitions 128 threads
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# over a 128x128 matrix. We need to figure out the exact
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# (tid, vid) -> (m, k) mapping analytically.
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# Let me print what we know about the TMEM load's thread mapping.
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# The layout_dst_tv_tiled is a Layout with shape (n_threads, n_vals).
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print(f"\n=== Analyzing TV layout for analytical construction ===")
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print(f"TV layout type: {type(tv)}")
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# Try to decompose it
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if hasattr(tv, 'shape'):
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print(f" shape: {tv.shape}")
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if hasattr(tv, 'stride'):
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print(f" stride: {tv.stride}")
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def test_cotiled_diag():
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print("=== make_cotiled_copy Diagnostic ===\n")
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hd = 64
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q = torch.randn(128, hd, 1, dtype=torch.bfloat16, device='cuda')
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k = torch.randn(128, hd, 1, dtype=torch.bfloat16, device='cuda')
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v = torch.randn(128, min(hd, 256), dtype=torch.bfloat16, device='cuda')
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c = torch.zeros(128, min(hd, 256), 1, dtype=torch.bfloat16, device='cuda')
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diag = SmemPDiag(head_dim=hd, s_k=128)
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stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)
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v_tile = v.unsqueeze(-1)
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mQ = ct.from_dlpack(q).mark_layout_dynamic(leading_dim=ct.get_leading_dim(q))
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mK = ct.from_dlpack(k).mark_layout_dynamic(leading_dim=ct.get_leading_dim(k))
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mV = ct.from_dlpack(v_tile).mark_layout_dynamic(leading_dim=ct.get_leading_dim(v_tile))
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mC = ct.from_dlpack(c).mark_layout_dynamic(leading_dim=ct.get_leading_dim(c))
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print('Compiling diagnostic kernel...', flush=True)
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compiled = cute.compile(diag, mQ, mK, mV, mC, stream)
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print('Running...', flush=True)
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compiled(mQ, mK, mV, mC, stream)
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torch.cuda.synchronize()
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print('Done.')
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if __name__ == '__main__':
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test_cotiled_diag()
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