233 lines
10 KiB
Python
233 lines
10 KiB
Python
"""
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D1.3 SMEM-P: Debug test that checks if P written to SMEM is read back correctly.
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Creates a simple test kernel that:
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1. Writes known values to sP via coordinate indexing
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2. Reads them back via pv_mma.make_fragment_A(sP)
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3. Compares the values
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"""
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import torch, math
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import cutlass, cutlass.cute as cute, cutlass.utils as utils
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from cutlass.cute.nvgpu import tcgen05, cpasync
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from cutlass import Float32, BFloat16, Int32, const_expr
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from cutlass.utils import LayoutEnum
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from cutlass.utils.tmem_allocator import find_tmem_tensor_col_offset
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import cutlass.torch as ct
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import cuda.bindings.driver as cuda
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class SmemPWriteReadTest:
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"""Test kernel: write P to sP, read back, verify."""
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def __init__(self, head_dim=64, s_k=128):
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self.head_dim = head_dim
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self.s_k = s_k
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self.pv_n_tile = min(head_dim, 256)
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self.qk_mma_tiler = (128, 128, 128 * 4)
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self.pv_mma_tiler = (128, self.pv_n_tile, 128)
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self.use_smem_p = True
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self.normalize = True
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self.acc_dtype = Float32
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self.qk_acc_dtype = Float32
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self.q_dtype = BFloat16
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self.o_dtype = BFloat16
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self.use_2cta_instrs = False
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self.cta_group = tcgen05.CtaGroup.ONE
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self.cluster_shape_mn = (1, 1)
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self.epilogue_warp_id = (0, 1, 2, 3)
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self.mma_warp_id = 4
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self.tma_warp_id = 5
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self.threads_per_cta = 192
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self.num_acc_stage = 1
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self.scale_softmax_log2 = 1.0 / math.sqrt(self.head_dim) * math.log2(math.e)
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self.kv_stage = 2
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self.q_stage = 1
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self.num_c_stage = 2
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self.c_layout = LayoutEnum.ROW_MAJOR
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self.tmem_p0_offset = -1
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self.tOrP0_offset = 0
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@cute.jit
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def __call__(self, q, k, v, c, stream):
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self.a_major = LayoutEnum.from_tensor(q).mma_major_mode()
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self.b_major = LayoutEnum.from_tensor(k).mma_major_mode()
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v_fmha = cute.make_tensor(
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v.iterator,
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cute.make_layout(
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(self.pv_n_tile, self.s_k, 1),
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stride=(1, self.pv_n_tile, self.pv_n_tile * self.s_k),
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),
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)
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self.v_major = LayoutEnum.from_tensor(v_fmha).mma_major_mode()
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qk_mma = utils.sm100.make_trivial_tiled_mma(
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self.q_dtype, self.q_dtype, self.a_major, self.b_major,
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self.qk_acc_dtype, self.cta_group, (128, 128), tcgen05.OperandSource.SMEM
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)
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pv_a_major = cute.nvgpu.OperandMajorMode.K
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pv_mma = utils.sm100.make_trivial_tiled_mma(
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self.q_dtype, self.q_dtype, pv_a_major, self.v_major,
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self.qk_acc_dtype, self.cta_group, (128, self.pv_n_tile),
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tcgen05.OperandSource.SMEM
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)
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# Setup
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qk_thr = qk_mma.get_slice(0)
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qk_as = qk_thr.partition_shape_C(self.qk_mma_tiler[:2])
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tStS = qk_thr.make_fragment_C(qk_as)
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pv_thr = pv_mma.get_slice(0)
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pv_as = pv_thr.partition_shape_C(self.pv_mma_tiler[:2])
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tOtO = pv_thr.make_fragment_C(pv_as)
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self.tmem_s0_offset = 0
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self.tmem_o0_offset = 0
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s_cols = self.qk_mma_tiler[1]
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o_cols = find_tmem_tensor_col_offset(tOtO)
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total = max(s_cols, o_cols)
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_n = 1
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while _n < total:
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_n *= 2
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self.num_tmem_alloc_cols = _n
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p_smem_s = utils.sm100.make_smem_layout_a(pv_mma, self.pv_mma_tiler, self.q_dtype, 1)
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q_smem_s = utils.sm100.make_smem_layout_a(qk_mma, self.qk_mma_tiler, self.q_dtype, self.q_stage)
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k_smem_s = utils.sm100.make_smem_layout_b(qk_mma, self.qk_mma_tiler, self.q_dtype, self.kv_stage)
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v_smem_s = utils.sm100.make_smem_layout_b(pv_mma, self.pv_mma_tiler, self.q_dtype, self.kv_stage)
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c_smem_s = utils.sm100.make_smem_layout_epi(self.o_dtype, self.c_layout, (128, self.pv_n_tile), 2)
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q_s = cute.slice_(q_smem_s, (None, None, None, 0))
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k_s = cute.slice_(k_smem_s, (None, None, None, 0))
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v_s = cute.slice_(v_smem_s, (None, None, None, 0))
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cta = cute.size(qk_mma.thr_id.shape)
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self.q_tx_bytes = cute.size_in_bytes(self.q_dtype, q_s) * cta
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self.kv_tx_bytes = (cute.size_in_bytes(self.q_dtype, k_s) + cute.size_in_bytes(self.q_dtype, v_s)) * cta
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tma_q, mQ = cute.nvgpu.make_tiled_tma_atom_A(
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utils.sm100.cluster_shape_to_tma_atom_A(self.cluster_shape_mn, qk_mma.thr_id),
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q, q_s, self.qk_mma_tiler, qk_mma, (1, 1, 1, 1)
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)
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tma_k, mK = cute.nvgpu.make_tiled_tma_atom_B(
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utils.sm100.cluster_shape_to_tma_atom_B(self.cluster_shape_mn, qk_mma.thr_id),
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k, k_s, self.qk_mma_tiler, qk_mma, (1, 1, 1, 1)
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)
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tma_v, mV = cute.nvgpu.make_tiled_tma_atom_B(
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utils.sm100.cluster_shape_to_tma_atom_B(self.cluster_shape_mn, pv_mma.thr_id),
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v_fmha, v_s, self.pv_mma_tiler, pv_mma, (1, 1, 1, 1)
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)
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epi_s = cute.select(c_smem_s, mode=[0, 1])
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tma_c, mC = cpasync.make_tiled_tma_atom(cpasync.CopyBulkTensorTileS2GOp(), c, epi_s, (128, self.pv_n_tile))
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self._kernel(qk_mma, pv_mma, tma_q, mQ, tma_k, mK, tma_v, mV, tma_c, mC,
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p_smem_s, q_smem_s, k_smem_s, v_smem_s, c_smem_s,
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tStS, tOtO, qk_thr, pv_thr).launch(
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grid=(1, 1, 1), block=[self.threads_per_cta, 1, 1], stream=stream
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)
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@cute.kernel
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def _kernel(self, qk_mma, pv_mma, tma_q, mQ, tma_k, mK, tma_v, mV, tma_c, mC,
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p_smem_s, q_smem_s, k_smem_s, v_smem_s, c_smem_s,
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tStS, tOtO, qk_thr, pv_thr):
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tidx, _, _ = cute.arch.thread_idx()
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warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())
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@cute.struct
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class SS:
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q_bar: cute.struct.MemRange[cutlass.Int64, self.q_stage * 2]
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kv_bar: cute.struct.MemRange[cutlass.Int64, self.kv_stage * 2]
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s_bar: cute.struct.MemRange[cutlass.Int64, 2]
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acc_bar: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage * 2]
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tmem_dealloc: cutlass.Int64
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holding: cutlass.Int32
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smem = utils.SmemAllocator()
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st = smem.allocate(SS)
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sQ = smem.allocate_tensor(element_type=self.q_dtype, layout=q_smem_s.outer, byte_alignment=128, swizzle=q_smem_s.inner)
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sK = smem.allocate_tensor(element_type=self.q_dtype, layout=k_smem_s.outer, byte_alignment=128, swizzle=k_smem_s.inner)
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sV = smem.allocate_tensor(element_type=self.q_dtype, layout=v_smem_s.outer, byte_alignment=128, swizzle=v_smem_s.inner)
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sP = smem.allocate_tensor(element_type=self.q_dtype, layout=p_smem_s.outer, byte_alignment=128, swizzle=p_smem_s.inner)
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# Only use softmax warps for this test
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if warp_idx < 4:
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# TMEM load partition for getting coordinates
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tmem_load_atom = cute.make_copy_atom(tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)), self.qk_acc_dtype)
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tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tStS)
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sfw_idx = tidx % (32 * len(self.epilogue_warp_id))
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thr_load = tiled_tmem_load.get_slice(sfw_idx)
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tTMEM_LOADtS = thr_load.partition_S(tStS)
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cS = cute.make_identity_tensor((self.qk_mma_tiler[0], self.qk_mma_tiler[1]))
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tScS = qk_thr.partition_C(cS)
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tTMEM_LOADcS = thr_load.partition_D(tScS)
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# Write known values to sP: value = m * 128 + k (the linear index)
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# Each thread writes its portion using coordinate indexing
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sP_stage = sP[(None, None, None, 0)]
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# PRINT: coordinates for thread 0
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if sfw_idx == 0:
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print(f"=== SMEM-P Write/Read Test ===")
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print(f"sP shape: {cute.shape(sP)}")
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print(f"sP_stage shape: {cute.shape(sP_stage)}")
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print(f"sP_stage layout: {sP_stage.layout}")
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print(f"tTMEM_LOADcS shape: {cute.shape(tTMEM_LOADcS)}")
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print(f"tTMEM_LOADcS layout: {tTMEM_LOADcS.layout}")
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# Print first few coordinates for thread 0
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for j0 in range(4):
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for j1 in range(4):
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coord = tTMEM_LOADcS[(j0, 0), j1, 0, 0]
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print(f" cS[{j0}, {j1}]: coord={coord}")
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# Write P values to SMEM
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for j0 in range(32):
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for j1 in range(4):
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coord = tTMEM_LOADcS[(j0, 0), j1, 0, 0]
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m_c = coord[0]
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k_c = coord[1]
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k0 = k_c % 16
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k1 = (k_c // 16) % 4
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k2 = k_c // 64
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# Write a known pattern: BF16(m_c * 128 + k_c)
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# Use a simple value that's easy to verify
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_val = BFloat16(1.0) # Just write 1.0 everywhere
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sP_stage[(m_c, k0), 0, (k1, k2)] = _val
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cute.arch.fence_proxy("async.shared", space="cta")
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# Now read back via PV MMA's fragment
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tCrP = pv_mma.make_fragment_A(sP)
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if sfw_idx == 0:
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print(f"tCrP shape: {cute.shape(tCrP)}")
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print(f"tCrP layout: {tCrP.layout}")
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# Print first few values read back
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for i in range(min(4, cute.size(tCrP, mode=[2]))):
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print(f" tCrP[0,0,{i},0] = {tCrP[0, 0, i, 0]}")
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def test_smem_p_write_read():
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hd = 64
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q = torch.randn(128, hd, 1, dtype=torch.bfloat16, device='cuda')
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k = torch.randn(128, hd, 1, dtype=torch.bfloat16, device='cuda')
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v = torch.randn(128, hd, dtype=torch.bfloat16, device='cuda')
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c = torch.zeros(128, hd, 1, dtype=torch.bfloat16, device='cuda')
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kern = SmemPWriteReadTest(head_dim=hd, s_k=128)
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stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)
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v_tile = v.unsqueeze(-1)
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mQ = ct.from_dlpack(q).mark_layout_dynamic(leading_dim=ct.get_leading_dim(q))
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mK = ct.from_dlpack(k).mark_layout_dynamic(leading_dim=ct.get_leading_dim(k))
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mV = ct.from_dlpack(v_tile).mark_layout_dynamic(leading_dim=ct.get_leading_dim(v_tile))
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mC = ct.from_dlpack(c).mark_layout_dynamic(leading_dim=ct.get_leading_dim(c))
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print('Compiling...', flush=True)
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compiled = cute.compile(kern, mQ, mK, mV, mC, stream)
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print('Running...', flush=True)
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compiled(mQ, mK, mV, mC, stream)
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torch.cuda.synchronize()
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print('Done.')
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if __name__ == '__main__':
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test_smem_p_write_read()
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