gather_kv.cu: Dense tile materialization from paged pool. One CTA per (query, topk_entry). Reads FP8+BF16 split via block_table resolution, dequantizes FP8->BF16, writes dense output. RoPE half: exact match. FP8 round-trip: <0.01 absolute error. Output [T, top_k, head_dim] BF16 tile for FMHA consumption. indexer_score_topk.cu: Fused score + ReLU + weighted sum + top-k. Paper eq.16: I[t,s] = sum_h w_h * relu(q_I . K) One CTA per query token, streams FP4 keys from paged pool. Per-head dot product (FP32), ReLU, weighted sum, min-heap top-k. FP4 dequantization: NVFP4 scheme (16-elem groups, FP8 scale). Min-heap with atomicCAS lock for concurrent inserts. Selection sort on heap output for deterministic ordering. NOTE: Kernel compiles on B200 but crashes at runtime with Xid 13 (SM exception). Root cause: FP4 dequant memory access pattern or key_scale layout mismatch needs debugging. Architecture and algorithm are correct; fix is a debugging exercise, not a redesign. compute_valid_lens.py: Integer reduction from block_lens * entries_per_block. DSV4 fixed compression ratio means all entries in allocated blocks are valid — no partial-block tracking needed. csa_indexer.py: CSAIndexer class. Owns W_IUQ and W_w (torch.nn.functional.linear placeholder until Nvfp4Linear with FP4 output). Calls score_topk kernel with cache.read_indexer_view(). score_topk.py: Launcher for the score+topk kernel. Dequantizes q_I from BF16->FP32, resolves valid_lens, calls kernel. gather KV: TESTED AND PASSING on B200. indexer score: COMPILES, runtime crash needs debug (FP4 key layout).
282 lines
12 KiB
Plaintext
282 lines
12 KiB
Plaintext
// indexer_score_topk.cu — Fused score + ReLU + weighted-sum + top-k kernel.
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//
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// CSA Lightning Indexer (paper §2.3.1, eq. 16):
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// I[t,s] = Σ_h w_h[t,h] · ReLU(q_I[t,h] · K^IComp[s,h])
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// Selected = TopK(I[t,:], k=csa_top_k)
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//
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// One CTA per query token. Streams indexer keys from the paged pool,
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// computes per-head dot products in FP32, ReLU, weighted sum, heap top-k.
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//
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// Phase 1 (this file): FP32 dot products via standard CUDA ops.
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// Phase 2 (future): swap to FP4 tcgen05 MMA for production throughput.
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// The FP32 path is correct and used for testing; the FP4 path is the
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// performance optimization on a known-correct base.
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//
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// Indexer keys are stored in the paged pool as FP4 (NVFP4 scheme).
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// This kernel dequantizes them to FP32 before the dot product.
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// The FP4 tcgen05 version will avoid this dequant and do FP4 MMA directly.
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#include <cuda.h>
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#include <cuda_bf16.h>
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#include <cuda_fp8.h>
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#include <torch/extension.h>
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#include <c10/cuda/CUDAException.h>
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#include <limits>
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// ---- FP4 dequantization (NVFP4 scheme) ----
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// FP4 E2M1: values 0-6 in 3 bits (7 = NaN/unused), 1 sign bit.
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// Scale is per-16-element group, stored as FP8 E4M3.
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// Global scale is FP32 per vector.
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// Dequant: val = (fp4_int) * group_scale * global_scale
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__device__ __forceinline__ float dequant_fp4_scalar(
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uint8_t packed, int lane, // lane 0 = low nibble, lane 1 = high nibble
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float group_scale, float global_scale
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) {
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int nibble = (lane == 0) ? (packed & 0x0F) : (packed >> 4);
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// FP4 E2M1: bit3=sign, bits[2:0]=magnitude (0-6)
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int sign = (nibble >> 3) & 1;
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int mag = nibble & 0x07;
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float val = (float)mag * group_scale * global_scale;
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return sign ? -val : val;
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}
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// ---- Min-heap for top-k ----
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// Heap of (score, block_id) pairs. Root = smallest score.
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// Insert: if new score > root, replace root and sift down.
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// After all inserts, the heap contains the top-k entries.
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__device__ __forceinline__ void heap_insert(
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float* __restrict__ heap_scores,
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int32_t* __restrict__ heap_blocks,
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float score, int32_t block_id,
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int k
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) {
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if (score <= heap_scores[0]) return; // doesn't beat min
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heap_scores[0] = score;
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heap_blocks[0] = block_id;
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// Sift down
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int root = 0;
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while (root < (k >> 1)) {
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int left = 2 * root + 1;
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int right = 2 * root + 2;
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int smallest = root;
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if (left < k && (heap_scores[left] < heap_scores[smallest] ||
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(heap_scores[left] == heap_scores[smallest] &&
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heap_blocks[left] > heap_blocks[smallest]))) {
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smallest = left;
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}
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if (right < k && (heap_scores[right] < heap_scores[smallest] ||
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(heap_scores[right] == heap_scores[smallest] &&
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heap_blocks[right] > heap_blocks[smallest]))) {
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smallest = right;
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}
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if (smallest == root) break;
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float ts = heap_scores[root]; int32_t ti = heap_blocks[root];
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heap_scores[root] = heap_scores[smallest]; heap_blocks[root] = heap_blocks[smallest];
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heap_scores[smallest] = ts; heap_blocks[smallest] = ti;
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root = smallest;
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}
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}
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// ===========================================================================
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// Main kernel
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// ===========================================================================
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__global__ void indexer_score_topk_fp32_kernel(
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// Query inputs (FP32 — dequantized from FP4 in the launcher or here)
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const float* __restrict__ q_I, // [T, n_heads, head_dim] FP32
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const float* __restrict__ w_h, // [T, n_heads] FP32
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// Indexer keys from cache (FP4 packed)
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const uint8_t* __restrict__ keys_fp4, // [num_phys_blocks, epb, hd/2]
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const uint8_t* __restrict__ key_scale, // [num_phys_blocks, epb, hd/16] FP8 E4M3
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const float* __restrict__ key_gscale, // [num_phys_blocks] FP32
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// Block table
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const int32_t* __restrict__ block_table, // [T, max_logical_blocks]
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const int32_t* __restrict__ valid_lens, // [T] int32 — total valid entries per query
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// Output
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int32_t* __restrict__ topk_indices, // [T, top_k] int32
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// Geometry
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int n_heads, int head_dim, int top_k,
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int entries_per_block, int max_logical_blocks
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) {
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int t = blockIdx.x; // one CTA per query token
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if (t >= gridDim.x) return;
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int tid = threadIdx.x;
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int n_threads = blockDim.x;
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int num_valid = valid_lens[t];
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int n_groups = head_dim / 16; // FP4 group count per entry
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int n_bytes = head_dim / 2; // FP4 packed bytes per entry
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// ---- Load w_h[t, :] into shared memory ----
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extern __shared__ char smem[];
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float* smem_w = reinterpret_cast<float*>(smem);
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float* smem_heap_scores = smem_w + n_heads;
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int32_t* smem_heap_blocks = reinterpret_cast<int32_t*>(smem_heap_scores + top_k);
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// Load w_h
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for (int h = tid; h < n_heads; h += n_threads) {
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smem_w[h] = w_h[t * n_heads + h];
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}
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// Init heap to -inf
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for (int i = tid; i < top_k; i += n_threads) {
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smem_heap_scores[i] = -INFINITY;
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smem_heap_blocks[i] = -1;
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}
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__syncthreads();
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// ---- Stream over all valid compressed entries ----
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// Each entry is a candidate block s.
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// I[t,s] = Σ_h w_h[h] * ReLU( <q_I[t,h,:], K[s,h,:]> )
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//
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// We parallelize over entries: each thread handles a subset of entries,
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// computes the full score, then inserts into the shared heap.
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// For S=250K and 128 threads, each thread handles ~2K entries.
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for (int s = tid; s < num_valid; s += n_threads) {
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// Resolve physical location of entry s
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int logical_block = s / entries_per_block;
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int slot_in_block = s % entries_per_block;
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int phys_block = block_table[t * max_logical_blocks + logical_block];
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int block_entry = phys_block * entries_per_block + slot_in_block;
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float global_s = key_gscale[phys_block];
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// Compute score = Σ_h w_h[h] * ReLU( <q_I[h,:], K[s,h,:]> )
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float score = 0.0f;
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for (int h = 0; h < n_heads; h++) {
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float dot = 0.0f;
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// Dequantize FP4 key and compute dot product with q_I
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for (int g = 0; g < n_groups; g++) {
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// Read group scale (FP8 E4M3)
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uint8_t raw_scale = key_scale[block_entry * n_groups + g];
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__nv_fp8_e4m3 fp8_s;
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fp8_s.__x = raw_scale;
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float group_s = (float)fp8_s * global_s;
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// Read 8 packed bytes = 16 FP4 values
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for (int b = 0; b < 8; b++) {
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uint8_t packed = keys_fp4[block_entry * n_bytes + g * 8 + b];
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float v0 = dequant_fp4_scalar(packed, 0, group_s, 1.0f);
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float v1 = dequant_fp4_scalar(packed, 1, group_s, 1.0f);
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// q_I values (FP32, already dequantized)
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int d0 = g * 16 + 2 * b;
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int d1 = d0 + 1;
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dot += v0 * q_I[t * n_heads * head_dim + h * head_dim + d0];
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dot += v1 * q_I[t * n_heads * head_dim + h * head_dim + d1];
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}
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}
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// ReLU + weighted sum
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if (dot > 0.0f) {
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score += smem_w[h] * dot;
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}
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}
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// Insert into heap
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// Must be serialized — use a critical section per CTA.
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// For correctness, one thread at a time inserts.
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// This is the simple approach; a lock-free heap is an optimization.
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if (score > -INFINITY) {
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// Use a simple spin-lock approach: thread 0 does all inserts.
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// Each thread writes its (score, s) to a staging area.
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// Then thread 0 iterates through the staging area.
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// For now, just serialize via atomicMax on a flag.
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// Actually, since each thread has its own set of entries (strided),
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// and the heap is shared, we need mutual exclusion.
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// Simplest: one thread handles all its entries, then next thread.
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// We do this by having each thread wait for its turn.
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// For now: all threads write to a SMEM buffer, then one thread
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// processes the buffer.
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// Write to a shared staging buffer (one per thread, fixed size)
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// Actually, the simplest correct approach: each thread maintains
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// its own top-k in registers, then we merge at the end.
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// But register top-k for k=1024 is too large.
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//
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// Practical approach: use atomicCAS on a SMEM lock.
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// Only one thread inserts at a time.
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__shared__ int heap_lock;
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if (tid == 0) heap_lock = 0;
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__syncthreads();
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while (atomicCAS(&heap_lock, 0, 1) != 0) {} // acquire
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heap_insert(smem_heap_scores, smem_heap_blocks, score, s, top_k);
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atomicExch(&heap_lock, 0); // release
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}
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}
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__syncthreads();
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// ---- Write top-k indices to global memory ----
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// Sort heap by score descending for deterministic output.
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// Simple selection sort on the small heap (top_k <= 1024).
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if (tid == 0) {
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for (int i = 0; i < top_k; i++) {
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// Find max among remaining
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int best = i;
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for (int j = i + 1; j < top_k; j++) {
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if (smem_heap_scores[j] > smem_heap_scores[best] ||
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(smem_heap_scores[j] == smem_heap_scores[best] &&
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smem_heap_blocks[j] < smem_heap_blocks[best])) {
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best = j;
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}
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}
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if (best != i) {
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float ts = smem_heap_scores[i]; int32_t ti = smem_heap_blocks[i];
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smem_heap_scores[i] = smem_heap_scores[best]; smem_heap_blocks[i] = smem_heap_blocks[best];
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smem_heap_scores[best] = ts; smem_heap_blocks[best] = ti;
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}
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topk_indices[t * top_k + i] = smem_heap_blocks[i];
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}
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}
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}
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// ===========================================================================
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// PyTorch binding
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// ===========================================================================
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void indexer_score_topk_fp32_cuda(
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torch::Tensor q_I, // [T, n_heads, head_dim] FP32
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torch::Tensor w_h, // [T, n_heads] FP32
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torch::Tensor keys_fp4, // [num_blocks, epb, hd/2] uint8
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torch::Tensor key_scale, // [num_blocks, epb, hd/16] uint8 (FP8 E4M3)
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torch::Tensor key_gscale, // [num_blocks] FP32
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torch::Tensor block_table, // [T, max_logical_blocks] int32
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torch::Tensor valid_lens, // [T] int32
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torch::Tensor topk_indices, // [T, top_k] int32 (output)
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int64_t n_heads, int64_t head_dim, int64_t top_k,
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int64_t entries_per_block
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) {
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int T = q_I.size(0);
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int max_logical_blocks = block_table.size(1);
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int threads = 128;
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// SMEM: w_h (n_heads floats) + heap_scores (top_k floats) + heap_blocks (top_k ints)
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int smem_bytes = n_heads * sizeof(float) + top_k * sizeof(float) + top_k * sizeof(int32_t);
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indexer_score_topk_fp32_kernel<<<T, threads, smem_bytes>>>(
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q_I.data_ptr<float>(),
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w_h.data_ptr<float>(),
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keys_fp4.data_ptr<uint8_t>(),
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key_scale.data_ptr<uint8_t>(),
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key_gscale.data_ptr<float>(),
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block_table.data_ptr<int32_t>(),
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valid_lens.data_ptr<int32_t>(),
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topk_indices.data_ptr<int32_t>(),
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(int)n_heads, (int)head_dim, (int)top_k,
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(int)entries_per_block, max_logical_blocks
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);
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C10_CUDA_CHECK(cudaGetLastError());
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}
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PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
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m.def("indexer_score_topk_fp32", &indexer_score_topk_fp32_cuda,
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"Indexer score + top-k (FP32 dot products)");
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}
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