173 lines
6.4 KiB
Plaintext
173 lines
6.4 KiB
Plaintext
/**
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* Test SW128 UMMA descriptor for QK GEMM.
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* If this works, we can switch from NONE to SW128 and then add TMA loads.
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*
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* SW128 swizzle: TMA produces data in a format that MMA can read directly.
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* The SMEM layout is different from the NONE (canonical) layout.
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*
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* Key difference:
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* NONE: SMEM is written manually in canonical core-matrix order
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* SW128: SMEM is written by TMA in 128-byte swizzled order
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*/
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#include <cuda_runtime.h>
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#include <cstdio>
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#include <cstring>
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#include <cmath>
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#include "dsv4/kernels/attention/fmha_common.cuh"
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#include "dsv4/kernels/attention/fmha_umma_desc.cuh"
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using namespace dsv4::kernels::attention;
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static bf16_t f32_to_bf16_host(float f) { uint32_t u; memcpy(&u,&f,4); return (uint16_t)(u>>16); }
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static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; memcpy(&f,&u,4); return f; }
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constexpr int HD = 16, SK = 128, BLOCK_MN = 128;
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constexpr int NKT_QK = HD / MMA_K_BF16;
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constexpr int TILE_SZ = BLOCK_MN * MMA_K_BF16;
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// The SW128 SMEM layout is what TMA produces when loading a (128, 16) BF16 tile.
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// For a 128×16 BF16 matrix with 128-byte swizzle:
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// The swizzle permutes the 128-byte sectors to avoid bank conflicts.
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// We need to write data in the SW128 layout for the MMA to read correctly.
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// From CUTLASS and the PTX spec, the SW128 layout for a (128, 16) BF16 tile:
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// Each 128-byte row is stored at address: row * 16 * 2 = row * 32 bytes
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// With SW128, the row address is XOR-swizzled with bits from the column index.
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// The exact formula depends on the swizzle pattern.
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// For now, let's test: use the NONE (canonical) layout we know works,
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// but with the SW128 descriptor. If the results are wrong, we know the
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// SMEM layout must change for SW128.
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__global__ void __launch_bounds__(128)
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test_sw128_qk(const bf16_t* q, const bf16_t* k,
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float* o_scalar, float scale)
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{
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const int tid = threadIdx.x, wid = tid / 32, lane = tid % 32;
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extern __shared__ char sbuf[];
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uint32_t* sTmemBase = (uint32_t*)sbuf;
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bf16_t* sQ0 = (bf16_t*)(((uintptr_t)(sbuf + 4) + 15) & ~(uintptr_t)15);
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bf16_t* sK0 = sQ0 + TILE_SZ;
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// Load Q and K in CANONICAL layout (same as working NONE path)
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for (int i = tid; i < TILE_SZ; i += 128) sQ0[i] = 0;
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for (int d = tid; d < MMA_K_BF16; d += 128) {
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int ck = d / 8, lc = d % 8;
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sQ0[ck * 16 * 64 + lc] = q[d];
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}
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for (int i = tid; i < TILE_SZ; i += 128) sK0[i] = 0;
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for (int r = 0; r < SK; r++) {
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for (int d = tid; d < MMA_K_BF16; d += 128) {
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int ck = d / 8, lc = d % 8;
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int tmn = r / 8, lr = r % 8;
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sK0[ck * 16 * 64 + tmn * 64 + lr * 8 + lc] = k[r * HD + d];
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}
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}
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__syncthreads();
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// TMEM alloc
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if (wid == 1) tmem_alloc(__cvta_generic_to_shared(sTmemBase), 128);
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__syncthreads();
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uint32_t tb = *sTmemBase;
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// QK GEMM with SW128 descriptor
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{
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// Try SW128 descriptor for Q
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uint64_t dq_sw128 = make_umma_desc_kmajor_sw128(__cvta_generic_to_shared(sQ0), BLOCK_MN);
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uint64_t dk_sw128 = make_umma_desc_kmajor_sw128(__cvta_generic_to_shared(sK0), BLOCK_MN);
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uint32_t idesc = make_idesc(BLOCK_MN, BLOCK_MN);
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if (tid == 0) umma_ss_f16(tb, dq_sw128, dk_sw128, idesc, false);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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__syncthreads();
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}
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// Read S from TMEM (row 0 only)
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if (wid == 0) {
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float s_vals[SK], row_max = -INFINITY;
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for (int n = 0; n < SK / 8; n++) {
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
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: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
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"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
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: "r"(tb + n*8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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if (lane == 0) for (int c=0;c<8;c++) {
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s_vals[n*8+c] = tmp[c] * scale;
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row_max = fmaxf(row_max, tmp[c] * scale);
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}
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}
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row_max = wmax(row_max);
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float row_sum = 0.0f;
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if (lane == 0) for (int j=0;j<SK;j++) {
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s_vals[j] = expf(s_vals[j] - row_max);
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row_sum += s_vals[j];
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}
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row_sum = wsum(row_sum);
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if (lane == 0) for (int j=0;j<SK;j++) s_vals[j] /= row_sum;
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// Compare with reference
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if (tid == 0) {
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printf("SW128 QK result (first 8 attention weights): ");
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for (int j=0;j<8;j++) printf("%.6f ", s_vals[j]);
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printf("\n");
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}
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}
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// Scalar reference
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if (tid == 0) {
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float s[SK];
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for (int j=0;j<SK;j++) {
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float dot = 0.0f;
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for (int d=0;d<HD;d++) dot += bf16_to_f32(q[d]) * bf16_to_f32(k[j*HD+d]);
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s[j] = dot * scale;
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}
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float mx = -INFINITY;
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for (int j=0;j<SK;j++) mx = fmaxf(mx, s[j]);
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float sm = 0.0f;
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for (int j=0;j<SK;j++) { s[j] = expf(s[j]-mx); sm += s[j]; }
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for (int j=0;j<SK;j++) s[j] /= sm;
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printf("Reference (first 8 attention weights): ");
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for (int j=0;j<8;j++) printf("%.6f ", s[j]);
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printf("\n");
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float cs=0,na=0,nb=0;
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// Can't compare directly since we need s_vals from another thread
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// Just print both and let human verify
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}
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if (wid == 0) tmem_dealloc(tb, 128);
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}
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int main() {
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printf("=== SW128 UMMA descriptor test (HD=16) ===\n");
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const float SCALE = 1.0f / sqrtf((float)HD);
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bf16_t* h_q = (bf16_t*)malloc(HD*sizeof(bf16_t));
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bf16_t* h_k = (bf16_t*)malloc(SK*HD*sizeof(bf16_t));
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srand(42);
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for (int d=0;d<HD;d++) h_q[d] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
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for (int i=0;i<SK*HD;i++) h_k[i] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
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bf16_t *d_q,*d_k;
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float* d_o_scalar;
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cudaMalloc(&d_q, HD*sizeof(bf16_t));
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cudaMalloc(&d_k, SK*HD*sizeof(bf16_t));
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cudaMalloc(&d_o_scalar, HD*sizeof(float));
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cudaMemcpy(d_q, h_q, HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
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cudaMemcpy(d_k, h_k, SK*HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
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int smem = (4+16 + TILE_SZ*2 + TILE_SZ*2 + 256 + 127) & ~127;
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test_sw128_qk<<<1, 128, smem>>>(d_q, d_k, d_o_scalar, SCALE);
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cudaError_t err = cudaDeviceSynchronize();
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if (err != cudaSuccess) { printf("CUDA ERROR: %s\n", cudaGetErrorString(err)); return 1; }
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cudaFree(d_q); cudaFree(d_k); cudaFree(d_o_scalar);
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free(h_q); free(h_k);
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return 0;
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}
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