163 lines
6.1 KiB
Plaintext
163 lines
6.1 KiB
Plaintext
/**
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* Minimal QK test: load Q0 and K0 into SMEM, do one MMA, read result.
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* HD=64, NKT=4, T=1, SK=128.
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*/
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#include <cuda_runtime.h>
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#include <cuda.h>
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#include <cstdio>
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#include <cmath>
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#include <cstdlib>
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#include <cstring>
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#ifndef HD_VAL
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#define HD_VAL 64
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#endif
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#include "dsv4/kernels/attention/fmha_common.cuh"
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#include "dsv4/kernels/attention/fmha_umma_desc.cuh"
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using namespace dsv4::kernels::attention;
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static bf16_t f32_to_bf16_host(float f) { uint32_t u; memcpy(&u,&f,4); return (uint16_t)(u>>16); }
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static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; memcpy(&f,&u,4); return f; }
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constexpr int HD = HD_VAL;
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constexpr int SK = 128;
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constexpr int NKT = HD / MMA_K_BF16;
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constexpr int CORES_MN = 16; // 128/8
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__global__ void __launch_bounds__(128)
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test_qk_minimal_kernel(float* __restrict__ out_s,
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const bf16_t* __restrict__ q, const bf16_t* __restrict__ k, int T, int s_k)
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{
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static constexpr int TILE_SZ = 128 * MMA_K_BF16;
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static constexpr int TMEM_N = (HD <= 128) ? 128 : 256;
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static constexpr int NUM_READS = SK / 8;
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const int tid = threadIdx.x;
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const int lane = tid % 32;
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// Simple 4-warp: warp 0 = load+softmax+MMA, warps 1-3 = softmax
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// ALL 128 threads participate in loading and MMA is called by tid==0
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// SMEM: sQ0 and sK0 are (128, 16) each
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extern __shared__ __align__(128) char sbuf[];
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size_t off = 0;
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uint32_t* sTmemBase = (uint32_t*)sbuf; off = 4;
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off = (off + 127) & ~(size_t)127;
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bf16_t* sQ0 = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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off = (off + 127) & ~(size_t)127;
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bf16_t* sK0 = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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if (tid < 32) tmem_alloc(__cvta_generic_to_shared(sTmemBase), TMEM_N);
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__syncthreads();
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uint32_t tb = *sTmemBase;
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for (int kt = 0; kt < NKT; kt++) {
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// Load Q sub-tile — all 128 threads participate
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for (int i = tid; i < TILE_SZ; i += 128) sQ0[i] = 0;
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for (int d = tid; d < MMA_K_BF16; d += 128) {
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int full_d = kt * MMA_K_BF16 + d;
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if (full_d < HD) {
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// Q has 1 row (T=1), row 0: cm=0, lr=0
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int ck = d/8, lc = d%8;
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sQ0[ck*CORES_MN*64 + 0*64 + 0*8 + lc] = q[full_d];
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}
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}
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__syncthreads();
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// Load K sub-tile — all 128 threads
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for (int i = tid; i < TILE_SZ; i += 128) sK0[i] = 0;
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for (int r = tid; r < s_k; r += 128) {
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for (int d = 0; d < MMA_K_BF16; d++) {
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int full_d = kt * MMA_K_BF16 + d;
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int ck = d/8, lc = d%8, cm = r/8, lr = r%8;
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sK0[ck*CORES_MN*64 + cm*64 + lr*8 + lc] = k[r * HD + full_d];
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}
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}
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__syncthreads();
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if (tid == 0) {
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uint32_t idesc = make_idesc(128, 128);
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uint64_t dq = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sQ0), 128);
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uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK0), 128);
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umma_ss_f16(tb, dq, dk, idesc, kt > 0);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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}
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__syncthreads();
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}
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asm volatile("fence.sc.gpu;" ::: "memory");
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__syncthreads();
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// TMEM read — ALL 32 lanes must participate (warp-collective)
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// For T=1, only lane 0's data is meaningful
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{
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for (int n = 0; n < NUM_READS; n++) {
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
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: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
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"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
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: "r"(tb + n * 8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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if (lane < T) {
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for (int c = 0; c < 8; c++) {
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int col = n * 8 + c;
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if (col < s_k) out_s[lane * s_k + col] = tmp[c];
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}
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}
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}
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}
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__syncthreads();
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// TMEM dealloc — warp 0 does it (must be warp-collective)
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if (tid < 32) tmem_dealloc(tb, TMEM_N);
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}
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int main() {
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printf("Minimal QK Test (HD=%d, SK=%d)\n", HD, SK);
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const int T = 1;
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bf16_t* h_q = (bf16_t*)calloc(T * HD, sizeof(bf16_t));
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bf16_t* h_k = (bf16_t*)calloc(SK * HD, sizeof(bf16_t));
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srand(42);
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for (int i = 0; i < T * HD; i++) h_q[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
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for (int i = 0; i < SK * HD; i++) h_k[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
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bf16_t *d_q, *d_k; float *d_out;
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cudaMalloc(&d_q, T * HD * sizeof(bf16_t));
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cudaMalloc(&d_k, SK * HD * sizeof(bf16_t));
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cudaMalloc(&d_out, 128 * SK * sizeof(float));
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cudaMemcpy(d_q, h_q, T * HD * sizeof(bf16_t), cudaMemcpyHostToDevice);
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cudaMemcpy(d_k, h_k, SK * HD * sizeof(bf16_t), cudaMemcpyHostToDevice);
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int smem = 4 + 128 + 128*16*2 + 128*16*2 + 4096;
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test_qk_minimal_kernel<<<1, 128, smem>>>(d_out, d_q, d_k, T, SK);
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cudaError_t err = cudaDeviceSynchronize();
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if (err != cudaSuccess) { printf("CUDA ERROR: %s\n", cudaGetErrorString(err)); return 1; }
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float* h_out = (float*)malloc(128 * SK * sizeof(float));
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cudaMemcpy(h_out, d_out, 128 * SK * sizeof(float), cudaMemcpyDeviceToHost);
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float scale = 1.0f / sqrtf((float)HD);
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int fail = 0; float max_rel = 0;
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for (int t = 0; t < T; t++) {
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for (int j = 0; j < SK; j++) {
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float dot = 0;
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for (int d = 0; d < HD; d++)
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dot += bf16_to_f32_host(h_q[t * HD + d]) * bf16_to_f32_host(h_k[j * HD + d]);
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float ref = dot * scale;
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float got = h_out[t * SK + j];
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float rel = fabsf(ref) > 1e-4f ? fabsf(got - ref) / fabsf(ref) : fabsf(got - ref);
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if (rel > max_rel) max_rel = rel;
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if (rel > 0.01f && fail < 5) printf(" t=%d j=%d: ref=%.6f got=%.6f\n", t, j, ref, got);
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if (rel > 0.01f) fail++;
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}
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}
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printf("Max relative error: %.6f, failures: %d\n", max_rel, fail);
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printf("Raw output[0,0..4]: ");
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for (int j = 0; j < 5; j++) printf("%.6f ", h_out[j]);
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printf("\n");
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printf("%s\n", fail == 0 ? "PASSED" : "FAILED");
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return fail == 0 ? 0 : 1;
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}
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