119 lines
4.4 KiB
Plaintext
119 lines
4.4 KiB
Plaintext
/**
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* Copy of working test_mma_ts.cu — exact same code.
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* If this crashes, the issue is the kernel function signature or SMEM layout.
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*/
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#include <cuda_runtime.h>
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#include <cstdio>
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#include <cmath>
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#include <cstdlib>
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#include <cstring>
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#include "dsv4/kernels/attention/fmha_common.cuh"
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#include "dsv4/kernels/attention/fmha_umma_desc.cuh"
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using namespace dsv4::kernels::attention;
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constexpr int BLOCK_MN = 128;
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__global__ void __launch_bounds__(128)
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test_mma_ts_copy()
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{
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const int tid = threadIdx.x, wid = tid / 32, lane = tid % 32;
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extern __shared__ char sbuf[];
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uint32_t* sTmemBase = (uint32_t*)sbuf;
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bf16_t* sV = (bf16_t*)(((uintptr_t)(sbuf + 4) + 15) & ~(uintptr_t)15);
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for (int i = tid; i < 16 * 16; i += 128) sV[i] = 0;
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__syncthreads();
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for (int i = tid; i < 16 * 16; i += 128) {
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int r = i / 16, c = i % 16;
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int ck = c / 8, lc = c % 8;
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int tmn = r / 8, lr = r % 8;
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sV[ck * 2 * 64 + tmn * 64 + lr * 8 + lc] = f32_to_bf16(2.0f);
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}
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__syncthreads();
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if (wid == 0) tmem_alloc(__cvta_generic_to_shared(sTmemBase), 64);
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__syncthreads();
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uint32_t tb = *sTmemBase;
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uint32_t tb_o = tb + 32;
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// PV GEMM FIRST (before QK), then QK
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// Write A = all 1.0 into TMEM columns 0-15
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if (wid == 0) {
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for (int n = 0; n < 16 / 8; n++) {
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float p0=1.0f, p1=1.0f, p2=1.0f, p3=1.0f;
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float p4=1.0f, p5=1.0f, p6=1.0f, p7=1.0f;
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asm volatile("tcgen05.st.sync.aligned.32x32b.x8.b32 [%0],{%1,%2,%3,%4,%5,%6,%7,%8};" :: "r"(tb+n*8),"f"(p0),"f"(p1),"f"(p2),"f"(p3),"f"(p4),"f"(p5),"f"(p6),"f"(p7));
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}
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tmem_fence_store();
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}
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__syncthreads();
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// MMA TS
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uint64_t dv = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sV), 16);
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uint32_t idesc = make_idesc(BLOCK_MN, 16);
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if (tid == 0) umma_ts_f16(tb_o, tb, dv, idesc, false);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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__syncthreads();
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// Read C from TMEM
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if (wid == 0) {
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float c_vals[16];
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for (int n = 0; n < 2; n++) {
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];" : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7]) : "r"(tb_o + n*8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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if (lane == 0) for (int c=0;c<8;c++) c_vals[n*8+c] = tmp[c];
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}
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if (lane == 0) {
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printf("C[0,0..7] after PV: ");
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for (int c=0;c<8;c++) printf("%.2f ", c_vals[c]);
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printf("(expect 16.0)\n");
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}
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}
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__syncthreads();
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// NOW do QK GEMM — does it crash after PV TS MMA?
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bf16_t* sQ = sV + 16 * 16;
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bf16_t* sK = sQ + 128 * 16 + 4096;
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for (int i = tid; i < 128 * 16; i += 128) { sQ[i] = 0; sK[i] = 0; }
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__syncthreads();
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for (int d = tid; d < 16; d += 128) { int ck=d/8,lc=d%8; sQ[ck*16*64+lc] = f32_to_bf16(1.0f); }
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for (int i = tid; i < 128*16; i += 128) {
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int r=i/16,c=i%16; int ck=c/8,lc=c%8,tmn=r/8,lr=r%8;
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sK[ck*16*64+tmn*64+lr*8+lc] = f32_to_bf16(1.0f);
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}
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__syncthreads();
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uint64_t dq = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sQ), 128);
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uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK), 128);
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uint32_t iqk = make_idesc(128, 128);
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// QK writes to tb + 64 (columns 64-191, separate from PV's columns 32-47)
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// Note: we only allocated 64 columns, so this will be OOB.
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// Let me increase TMEM to 256 and write QK to tb + 128
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if (lane == 0) umma_ss_f16(tb + 64, dq, dk, iqk, false);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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__syncthreads();
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if (wid == 0) {
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];" : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7]) : "r"(tb));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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if (lane == 0) printf("S[0,0] after QK (post-PV): %.2f (expect 16.0)\n", tmp[0]);
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}
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if (wid == 0) tmem_dealloc(tb, 64);
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}
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int main() {
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printf("=== MMA TS Copy Test ===\n");
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int smem = (4 + 16 + 16*16*2 + 256 + 127) & ~127;
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test_mma_ts_copy<<<1, 128, smem>>>();
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cudaError_t err = cudaDeviceSynchronize();
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if (err != cudaSuccess) { printf("CUDA ERROR: %s\n", cudaGetErrorString(err)); return 1; }
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printf("PASS\n");
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return 0;
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}
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