283 lines
11 KiB
Plaintext
283 lines
11 KiB
Plaintext
/**
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* Debug HD=64 PV precision — compare register-math PV vs SS MMA PV
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* to isolate where the 0.931 cosine error comes from.
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*/
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#include <cuda_runtime.h>
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#include <cstdio>
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#include <cmath>
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#include <cstdlib>
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#include <cstring>
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#include "dsv4/kernels/attention/fmha_common.cuh"
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#include "dsv4/kernels/attention/fmha_umma_desc.cuh"
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using namespace dsv4::kernels::attention;
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static bf16_t f32_to_bf16_host(float f) { uint32_t u; memcpy(&u,&f,4); return (uint16_t)(u>>16); }
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static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; memcpy(&f,&u,4); return f; }
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constexpr int HD = 64, SK = 128, BLOCK_MN = 128;
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constexpr int NKT_QK = HD / MMA_K_BF16; // 4
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constexpr int NKT_PV = SK / MMA_K_BF16; // 8
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constexpr int TILE_SZ = BLOCK_MN * MMA_K_BF16; // 2048 BF16
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constexpr int V_TILE_SZ = (HD / 8) * 2 * 64; // 1024 BF16
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__global__ void __launch_bounds__(128)
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test_fmha_hd64_debug(const bf16_t* q, const bf16_t* k, const bf16_t* v,
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bf16_t* o_mma, float* o_ref, float* o_regmath,
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float scale)
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{
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const int tid = threadIdx.x, wid = tid / 32, lane = tid % 32;
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extern __shared__ char sbuf[];
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uint32_t* sTmemBase = (uint32_t*)sbuf;
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bf16_t* sQ0 = (bf16_t*)(((uintptr_t)(sbuf + 4) + 15) & ~(uintptr_t)15);
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bf16_t* sK0 = sQ0 + NKT_QK * TILE_SZ;
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bf16_t* sPk = (bf16_t*)(((uintptr_t)(sK0 + NKT_QK * TILE_SZ) + 127) & ~(uintptr_t)127);
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bf16_t* sV = (bf16_t*)(((uintptr_t)(sPk + TILE_SZ) + 127) & ~(uintptr_t)127);
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float* s_p_vals = (float*)(sV + NKT_PV * V_TILE_SZ);
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// Load Q K-tiles
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for (int kt = 0; kt < NKT_QK; kt++) {
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bf16_t* sq = sQ0 + kt * TILE_SZ;
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for (int i = tid; i < TILE_SZ; i += 128) sq[i] = 0;
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for (int d = tid; d < MMA_K_BF16; d += 128) {
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int ck = d / 8, lc = d % 8;
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sq[ck * 16 * 64 + lc] = q[kt * MMA_K_BF16 + d];
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}
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}
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// Load K K-tiles
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for (int kt = 0; kt < NKT_QK; kt++) {
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bf16_t* sk = sK0 + kt * TILE_SZ;
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for (int i = tid; i < TILE_SZ; i += 128) sk[i] = 0;
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for (int r = 0; r < SK; r++) {
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for (int d = tid; d < MMA_K_BF16; d += 128) {
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int ck = d / 8, lc = d % 8;
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int tmn = r / 8, lr = r % 8;
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sk[ck * 16 * 64 + tmn * 64 + lr * 8 + lc] = k[r * HD + kt * MMA_K_BF16 + d];
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}
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}
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}
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// Load V K-tiles
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for (int kt = 0; kt < NKT_PV; kt++) {
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bf16_t* sv = sV + kt * V_TILE_SZ;
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for (int i = tid; i < V_TILE_SZ; i += 128) sv[i] = 0;
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for (int d = tid; d < HD; d += 128) {
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for (int lr = 0; lr < MMA_K_BF16; lr++) {
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int r = kt * MMA_K_BF16 + lr;
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int g_mn = d / 8, g_k = lr / 8;
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int llr = d % 8, lc = lr % 8;
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sv[g_k * 8 * 64 + g_mn * 64 + llr * 8 + lc] = v[d * SK + r];
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}
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}
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}
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__syncthreads();
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// TMEM alloc
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if (wid == 1) tmem_alloc(__cvta_generic_to_shared(sTmemBase), 128);
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__syncthreads();
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uint32_t tb = *sTmemBase;
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// ===== QK GEMM (4 K-tiles) =====
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{
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uint32_t idesc = make_idesc(BLOCK_MN, BLOCK_MN);
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for (int kt = 0; kt < NKT_QK; kt++) {
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bf16_t* sq = sQ0 + kt * TILE_SZ;
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bf16_t* sk = sK0 + kt * TILE_SZ;
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uint64_t dq = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sq), BLOCK_MN);
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uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sk), BLOCK_MN);
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if (tid == 0) umma_ss_f16(tb, dq, dk, idesc, kt > 0);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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__syncthreads();
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}
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}
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// ===== Softmax (warp 0, row 0 only for T=1 decode) =====
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if (wid == 0) {
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float s_vals[SK], row_max = -INFINITY;
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for (int n = 0; n < SK / 8; n++) {
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
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: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
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"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
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: "r"(tb + n*8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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if (lane == 0) for (int c=0;c<8;c++) {
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s_vals[n*8+c] = tmp[c] * scale;
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row_max = fmaxf(row_max, tmp[c] * scale);
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}
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}
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row_max = wmax(row_max);
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float row_sum = 0.0f;
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if (lane == 0) for (int j=0;j<SK;j++) {
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s_vals[j] = expf(s_vals[j] - row_max);
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row_sum += s_vals[j];
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}
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row_sum = wsum(row_sum);
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if (lane == 0) for (int j=0;j<SK;j++) s_vals[j] /= row_sum;
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if (lane == 0) for (int j=0;j<SK;j++) s_p_vals[j] = s_vals[j];
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}
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__syncthreads();
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// ===== PV Method 1: Register math (FP32, proven correct) =====
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if (tid == 0) {
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for (int d = 0; d < HD; d++) {
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float ov = 0.0f;
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for (int j = 0; j < SK; j++) ov += s_p_vals[j] * bf16_to_f32(v[d * SK + j]);
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o_regmath[d] = ov;
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}
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}
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// ===== PV Method 2: SS MMA with BLOCK_MN_B=64 =====
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{
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uint32_t idesc_pv = make_idesc(BLOCK_MN, HD); // (128, 64)
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for (int kt = 0; kt < NKT_PV; kt++) {
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// Fill sPk from s_p_vals
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for (int i = tid; i < TILE_SZ; i += 128) sPk[i] = 0;
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if (tid < 16) {
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int c = tid;
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int ck = c / 8, lc = c % 8;
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sPk[ck * 16 * 64 + 0 * 64 + 0 * 8 + lc] = f32_to_bf16(s_p_vals[kt * MMA_K_BF16 + c]);
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}
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__syncthreads();
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bf16_t* sv = sV + kt * V_TILE_SZ;
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uint64_t dp = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sPk), BLOCK_MN);
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uint64_t dv = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sv), HD);
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if (tid == 0) umma_ss_f16(tb, dp, dv, idesc_pv, kt > 0);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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__syncthreads();
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}
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}
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// Read MMA output from TMEM
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if (wid == 0) {
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float o_vals[HD];
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for (int n = 0; n < HD / 8; n++) {
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
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: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
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"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
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: "r"(tb + n*8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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if (lane == 0) for (int c=0;c<8;c++) o_vals[n*8+c] = tmp[c];
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}
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if (lane == 0) for (int d=0;d<HD;d++) o_mma[d] = f32_to_bf16(o_vals[d]);
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}
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__syncthreads();
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// Scalar reference
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if (tid == 0) {
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float s[SK];
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for (int j=0;j<SK;j++) {
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float dot = 0.0f;
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for (int d=0;d<HD;d++) dot += bf16_to_f32(q[d]) * bf16_to_f32(k[j*HD+d]);
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s[j] = dot * scale;
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}
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float mx = -INFINITY;
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for (int j=0;j<SK;j++) mx = fmaxf(mx, s[j]);
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float sm = 0.0f;
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for (int j=0;j<SK;j++) { s[j] = expf(s[j]-mx); sm += s[j]; }
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for (int j=0;j<SK;j++) s[j] /= sm;
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for (int d=0;d<HD;d++) {
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float ov = 0.0f;
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for (int j=0;j<SK;j++) ov += s[j] * bf16_to_f32(v[d*SK+j]);
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o_ref[d] = ov;
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}
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}
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if (wid == 0) tmem_dealloc(tb, 128);
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}
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int main() {
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printf("=== Debug HD=64 PV: register-math vs SS MMA ===\n");
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const float SCALE = 1.0f / sqrtf((float)HD);
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bf16_t* h_q = (bf16_t*)malloc(HD*sizeof(bf16_t));
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bf16_t* h_k = (bf16_t*)malloc(SK*HD*sizeof(bf16_t));
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bf16_t* h_v = (bf16_t*)malloc(HD*SK*sizeof(bf16_t));
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bf16_t* h_o_mma = (bf16_t*)calloc(HD, sizeof(bf16_t));
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float* h_o_ref = (float*)calloc(HD, sizeof(float));
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float* h_o_regmath = (float*)calloc(HD, sizeof(float));
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srand(42);
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for (int d=0;d<HD;d++) h_q[d] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
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for (int i=0;i<SK*HD;i++) h_k[i] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
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for (int i=0;i<HD*SK;i++) h_v[i] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
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bf16_t *d_q,*d_k,*d_v,*d_o_mma; float *d_o_ref, *d_o_regmath;
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cudaMalloc(&d_q, HD*sizeof(bf16_t));
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cudaMalloc(&d_k, SK*HD*sizeof(bf16_t));
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cudaMalloc(&d_v, HD*SK*sizeof(bf16_t));
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cudaMalloc(&d_o_mma, HD*sizeof(bf16_t));
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cudaMalloc(&d_o_ref, HD*sizeof(float));
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cudaMalloc(&d_o_regmath, HD*sizeof(float));
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cudaMemcpy(d_q, h_q, HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
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cudaMemcpy(d_k, h_k, SK*HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
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cudaMemcpy(d_v, h_v, HD*SK*sizeof(bf16_t), cudaMemcpyHostToDevice);
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int smem = (4+16 + NKT_QK*TILE_SZ*2 + NKT_QK*TILE_SZ*2 + TILE_SZ*2 + NKT_PV*V_TILE_SZ*2 + SK*4 + 256 + 127) & ~127;
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printf("SMEM: %d bytes (%.1f KB)\n", smem, smem/1024.0f);
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cudaFuncSetAttribute(test_fmha_hd64_debug, cudaFuncAttributeMaxDynamicSharedMemorySize, smem);
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test_fmha_hd64_debug<<<1, 128, smem>>>(d_q, d_k, d_v, d_o_mma, d_o_ref, d_o_regmath, SCALE);
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cudaError_t err = cudaDeviceSynchronize();
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if (err != cudaSuccess) { printf("CUDA ERROR: %s\n", cudaGetErrorString(err)); return 1; }
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cudaMemcpy(h_o_mma, d_o_mma, HD*sizeof(bf16_t), cudaMemcpyDeviceToHost);
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cudaMemcpy(h_o_ref, d_o_ref, HD*sizeof(float), cudaMemcpyDeviceToHost);
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cudaMemcpy(h_o_regmath, d_o_regmath, HD*sizeof(float), cudaMemcpyDeviceToHost);
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// Compare register-math PV vs reference
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printf("\n--- Register-math PV vs FP32 reference ---\n");
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float cs_reg = 0, na_reg = 0, nb_reg = 0;
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for (int d=0;d<HD;d++) {
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float a = h_o_regmath[d], b = h_o_ref[d];
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cs_reg += a*b; na_reg += a*a; nb_reg += b*b;
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}
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cs_reg /= (sqrtf(na_reg)*sqrtf(nb_reg)+1e-10f);
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printf("Cosine: %.8f\n", cs_reg);
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// Compare MMA PV vs reference
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printf("\n--- MMA PV vs FP32 reference (all 64 elements) ---\n");
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for (int d=0;d<HD;d++) printf(" MMA[%2d]=%10.6f ref[%2d]=%10.6f ratio=%.4f\n",
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d, bf16_to_f32_host(h_o_mma[d]), d, h_o_ref[d],
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fabsf(h_o_ref[d])>1e-6f ? bf16_to_f32_host(h_o_mma[d])/h_o_ref[d] : 0);
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float cs_mma = 0, na_mma = 0, nb_mma = 0;
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for (int d=0;d<HD;d++) {
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float a = bf16_to_f32_host(h_o_mma[d]), b = h_o_ref[d];
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if (fabsf(b)>1e-4f) { cs_mma += a*b; na_mma += a*a; nb_mma += b*b; }
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}
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cs_mma /= (sqrtf(na_mma)*sqrtf(nb_mma)+1e-10f);
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printf("Filtered cosine: %.8f\n", cs_mma);
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// Compare MMA PV vs register-math PV
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printf("\n--- MMA PV vs register-math PV ---\n");
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float cs_cmp = 0, na_cmp = 0, nb_cmp = 0;
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for (int d=0;d<HD;d++) {
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float a = bf16_to_f32_host(h_o_mma[d]), b = h_o_regmath[d];
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cs_cmp += a*b; na_cmp += a*a; nb_cmp += b*b;
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}
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cs_cmp /= (sqrtf(na_cmp)*sqrtf(nb_cmp)+1e-10f);
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printf("Cosine: %.8f\n", cs_cmp);
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// Check if MMA output is proportional to reference (scale factor issue)
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float ratio_sum = 0; int rc = 0;
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for (int d=0;d<HD;d++) {
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float a = bf16_to_f32_host(h_o_mma[d]), b = h_o_ref[d];
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if (fabsf(b)>1e-6f) { ratio_sum += a/b; rc++; }
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}
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float avg_ratio = rc>0 ? ratio_sum/rc : 0;
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printf("Average MMA/ref ratio: %.6f\n", avg_ratio);
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printf("\nTest %s\n", cs_cmp > 0.999f ? "PASSED" : "FAILED");
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cudaFree(d_q); cudaFree(d_k); cudaFree(d_v);
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cudaFree(d_o_mma); cudaFree(d_o_ref); cudaFree(d_o_regmath);
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free(h_q); free(h_k); free(h_v); free(h_o_mma); free(h_o_ref); free(h_o_regmath);
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return cs_cmp > 0.999f ? 0 : 1;
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}
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