biondizzle 9c43c69a4c wip: fused SwiGLU Stage 1 - SiLU in registers (full acc_vec) ...

Stage 1 of the fused epilogue: applies SiLU (x * sigmoid(x)) to the
full accumulator register tensor before writing BF16 to C.

This validates that cute.exp and element-wise FP32 operations work
on CuTe register tensors in the epilogue. The gate/up pairing is
not yet implemented (Stage 2).

The fused_swiglu flag is const_expr(0) by default, so the standard
epilogue path is unchanged unless the flag is enabled.

2026-05-20 03:07:02 +00:00

..

blockscaled_gemm

refactor: copy CuTeDSL kernel into repo with local imports

2026-05-16 02:57:54 +00:00

moe

wip: fused SwiGLU Stage 1 - SiLU in registers (full acc_vec)

2026-05-20 03:07:02 +00:00

__init__.py

refactor: copy CuTeDSL kernel into repo with local imports

2026-05-16 02:57:54 +00:00