biondizzle 902bda5c31 D1: align P store and PV A-fragment layouts via tP ...

Key insight: tP (PV A-fragment base) used p_tmem_s.outer layout,
but P store used QK C-fragment composition layout. These diverge at hd>64.

Fix: tP now uses the same QK C-fragment composition layout (tStP_layout)
as the P store. PV A-fragment is derived from tP, so it automatically
uses the same layout. No double-offset since tP includes P offset.

2026-05-23 03:40:10 +00:00

..

attention

D1: align P store and PV A-fragment layouts via tP

2026-05-23 03:40:10 +00:00

cache

KV Cache: schema, allocator, pools, manager, append_swa kernel

2026-05-22 00:08:38 +00:00

compressor

Restructure: cutedsl/ -> dsv4/ with proper layering

2026-05-21 17:30:44 +00:00

cuda

Fix indexer score kernel: use static shared memory, correct FP4 head offsets

2026-05-22 01:45:05 +00:00

decode

Restructure: cutedsl/ -> dsv4/ with proper layering

2026-05-21 17:30:44 +00:00

gemm

Restructure: cutedsl/ -> dsv4/ with proper layering

2026-05-21 17:30:44 +00:00

indexer

Indexer: score+topk kernel, gather KV, compute_valid_lens

2026-05-22 01:20:39 +00:00

router

Router: Blackwell-native fused decode kernel — real CuTeDSL implementation

2026-05-21 22:04:20 +00:00

__init__.py

Restructure: cutedsl/ -> dsv4/ with proper layering

2026-05-21 17:30:44 +00:00