532 lines
32 KiB
Python
532 lines
32 KiB
Python
"""FMHA kernel: QK -> online softmax -> PV (CuTeDSL, Blackwell SM100).
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Migrated from tests/unit/test_fmha_v3_stage_c.py — Stage C proven path.
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P stored to TMEM via register bridge, PV reads from TMEM.
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O rescale via correction_rescale atoms, O normalization via TMEM round-trip.
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"""
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import torch, cutlass, cutlass.cute as cute, cutlass.utils as utils, cutlass.pipeline as pipeline
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from cutlass.cute.nvgpu import cpasync, tcgen05
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from cutlass import Float32, BFloat16, Int32, Boolean, const_expr
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from cutlass.utils import LayoutEnum
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from cutlass.utils.tmem_allocator import find_tmem_tensor_col_offset
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from cutlass.utils.blackwell_helpers import get_smem_store_op
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import cuda.bindings.driver as cuda
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import cutlass.torch as ct
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import math
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def _transform_partitioned_tensor_layout(tensor):
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"""Transform MMA layout: ((ATOM_M, ATOM_N), MMA_M, MMA_N, ...rest)
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-> ((ATOM_M, MMA_M), (ATOM_N, MMA_N), ...rest).
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Same as CUTLASS utils.gemm.sm100.transform_partitioned_tensor_layout."""
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layout = tensor.layout; shape = layout.shape; stride = layout.stride
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new_shape = ((shape[0][0], shape[1]), (shape[0][1], shape[2]), *shape[3:])
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new_stride = ((stride[0][0], stride[1]), (stride[0][1], stride[2]), *stride[3:])
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return cute.make_tensor(tensor.iterator, cute.make_layout(shape=new_shape, stride=new_stride))
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class FmhaKernel:
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def __init__(self, head_dim=64, s_k=128, scale_softmax=None, use_smem_p=None, normalize=True):
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self.head_dim = head_dim
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self.s_k = s_k
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self.n_kv_tiles = s_k // 128
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self.pv_n_tile = min(head_dim, 256) # tcgen05 MMA max N=256
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self.n_pv_tiles = head_dim // self.pv_n_tile
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self.use_smem_p = use_smem_p if use_smem_p is not None else (head_dim > 64)
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self.normalize = normalize # D5a: False = emit un-normalized O + lse
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self.acc_dtype = Float32; self.qk_acc_dtype = Float32
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self.q_dtype = BFloat16; self.o_dtype = BFloat16; self.c_dtype = BFloat16
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self.use_2cta_instrs = False; self.epilog_sync_bar_id = 1
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self.cluster_shape_mn = (1, 1); self.cta_group = tcgen05.CtaGroup.ONE
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self.epilogue_warp_id = (0,1,2,3); self.mma_warp_id = 4; self.tma_warp_id = 5
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self.threads_per_cta = 192; self.num_c_stage = 2
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self.kv_stage = 2; self.q_stage = 1; self.num_c_stage = 2
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self.scale_softmax = scale_softmax if scale_softmax is not None else 1.0 / math.sqrt(self.head_dim)
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self.scale_softmax_log2 = self.scale_softmax * math.log2(math.e)
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def _setup(self, qk_mma, pv_mma):
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qk_ik = cute.size(qk_mma.shape_mnk, mode=[2])
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self.qk_mma_tiler = (128, 128, qk_ik * 4)
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pv_ik = cute.size(pv_mma.shape_mnk, mode=[2])
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self.pv_mma_tiler = (128, self.pv_n_tile, pv_ik * (128 // pv_ik))
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self.mma_tiler = self.qk_mma_tiler
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self.cluster_layout_vmnk = cute.tiled_divide(cute.make_layout((1,1,1)), (qk_mma.thr_id.shape,))
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self.cta_tile_shape_mnk = (self.qk_mma_tiler[0]//cute.size(qk_mma.thr_id.shape), self.pv_n_tile, self.qk_mma_tiler[2])
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self.c_layout = LayoutEnum.ROW_MAJOR
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self.epi_tile = utils.sm100.compute_epilogue_tile_shape(self.cta_tile_shape_mnk, False, self.c_layout, self.o_dtype)
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self.num_ab_stage = 1; self.num_acc_stage = 1
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self.q_smem_s = utils.sm100.make_smem_layout_a(qk_mma, self.qk_mma_tiler, self.q_dtype, self.q_stage)
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self.k_smem_s = utils.sm100.make_smem_layout_b(qk_mma, self.qk_mma_tiler, self.q_dtype, self.kv_stage)
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self.v_smem_s = utils.sm100.make_smem_layout_b(pv_mma, self.pv_mma_tiler, self.q_dtype, self.kv_stage)
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self.c_smem_s = utils.sm100.make_smem_layout_epi(self.o_dtype, self.c_layout, self.epi_tile, 2)
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self.p_tmem_s = utils.sm100.make_smem_layout_a(pv_mma, self.pv_mma_tiler, self.q_dtype, 1)
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# P SMEM layout (PV A-operand) — used for SMEM-P path
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self.p_smem_s = utils.sm100.make_smem_layout_a(pv_mma, self.pv_mma_tiler, self.q_dtype, 1)
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qk_thr = qk_mma.get_slice(0); qk_as = qk_thr.partition_shape_C(self.qk_mma_tiler[:2])
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tStS = qk_thr.make_fragment_C(qk_as)
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pv_thr = pv_mma.get_slice(0); pv_as = pv_thr.partition_shape_C(self.pv_mma_tiler[:2])
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tOtO = pv_thr.make_fragment_C(pv_as)
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self.tmem_s0_offset = 0
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if not self.use_smem_p:
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# TMEM-P: S at 0, P at 32, O after P and S
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self.tmem_p0_offset = 32
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p_cols_fp32 = self.pv_mma_tiler[2] * self.q_dtype.width // self.qk_acc_dtype.width
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p_end = self.tmem_p0_offset + p_cols_fp32
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s_cols = self.qk_mma_tiler[1]
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o_after = max(s_cols, p_end)
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self.tmem_o0_offset = ((o_after + 31) // 32) * 32
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o_cols = find_tmem_tensor_col_offset(tOtO)
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total = self.tmem_o0_offset + o_cols
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else:
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# SMEM-P: P not in TMEM. S and O share TMEM (sequential).
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self.tmem_p0_offset = -1 # unused
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self.tmem_o0_offset = 0
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s_cols = self.qk_mma_tiler[1]
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o_cols = find_tmem_tensor_col_offset(tOtO)
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total = max(s_cols, o_cols)
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self.num_tmem_alloc_cols = 1
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while self.num_tmem_alloc_cols < total:
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self.num_tmem_alloc_cols *= 2
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# tOrP0 offset: BF16 elements from TMEM base to P0 (TMEM-P only)
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# = tmem_p0_offset * (FP32_width / BF16_width) if TMEM-P, else 0
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self.tOrP0_offset = max(self.tmem_p0_offset, 0) * 2 # Python int
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cta = cute.size(qk_mma.thr_id.shape)
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q_s = cute.slice_(self.q_smem_s,(None,None,None,0))
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k_s = cute.slice_(self.k_smem_s,(None,None,None,0))
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v_s = cute.slice_(self.v_smem_s,(None,None,None,0))
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self.q_tx_bytes = cute.size_in_bytes(self.q_dtype, q_s) * cta
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self.kv_tx_bytes = (cute.size_in_bytes(self.q_dtype, k_s) +
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cute.size_in_bytes(self.q_dtype, v_s)) * cta
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@cute.jit
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def __call__(self, q, k, v, c, stream, lse=None):
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self.q_dtype = q.element_type; self.o_dtype = c.element_type; self.c_dtype = self.o_dtype
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self.a_major = LayoutEnum.from_tensor(q).mma_major_mode()
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self.b_major = LayoutEnum.from_tensor(k).mma_major_mode()
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v_fmha = cute.make_tensor(
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v.iterator,
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cute.make_layout(
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(self.pv_n_tile, self.s_k, 1),
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stride=(1, self.pv_n_tile, self.pv_n_tile * self.s_k),
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),
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)
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self.v_major = LayoutEnum.from_tensor(v_fmha).mma_major_mode()
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self.c_layout = LayoutEnum.from_tensor(c)
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qk_mma = utils.sm100.make_trivial_tiled_mma(self.q_dtype, self.q_dtype, self.a_major, self.b_major, self.qk_acc_dtype, self.cta_group, (128,128), tcgen05.OperandSource.SMEM)
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pv_a_major = self.a_major if self.use_smem_p else cute.nvgpu.OperandMajorMode.K
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pv_source = tcgen05.OperandSource.SMEM if self.use_smem_p else tcgen05.OperandSource.TMEM
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pv_mma = utils.sm100.make_trivial_tiled_mma(self.q_dtype, self.q_dtype, pv_a_major, self.v_major, self.qk_acc_dtype, self.cta_group, (128,self.pv_n_tile), pv_source)
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self._setup(qk_mma, pv_mma)
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q_s = cute.slice_(self.q_smem_s,(None,None,None,0)); k_s = cute.slice_(self.k_smem_s,(None,None,None,0)); v_s = cute.slice_(self.v_smem_s,(None,None,None,0))
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tma_q,mQ = cute.nvgpu.make_tiled_tma_atom_A(utils.sm100.cluster_shape_to_tma_atom_A(self.cluster_shape_mn,qk_mma.thr_id),q,q_s,self.qk_mma_tiler,qk_mma,self.cluster_layout_vmnk.shape)
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tma_k,mK = cute.nvgpu.make_tiled_tma_atom_B(utils.sm100.cluster_shape_to_tma_atom_B(self.cluster_shape_mn,qk_mma.thr_id),k,k_s,self.qk_mma_tiler,qk_mma,self.cluster_layout_vmnk.shape)
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tma_v,mV = cute.nvgpu.make_tiled_tma_atom_B(utils.sm100.cluster_shape_to_tma_atom_B(self.cluster_shape_mn,pv_mma.thr_id),v_fmha,v_s,self.pv_mma_tiler,pv_mma,self.cluster_layout_vmnk.shape)
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epi_s = cute.select(self.c_smem_s,mode=[0,1])
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tma_c,mC = cpasync.make_tiled_tma_atom(cpasync.CopyBulkTensorTileS2GOp(),c,epi_s,self.epi_tile)
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# Always create a valid mLSE tensor for the kernel.
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# CuTeDSL doesn't support None parameters in @cute.kernel.
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# For normalize=True, mLSE is unused (dead-code-eliminated by compiler).
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if const_expr(lse is None):
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lse = cute.make_tensor(c.iterator, cute.make_layout((1,), stride=(0,)))
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self._kernel(qk_mma,pv_mma,tma_q,mQ,tma_k,mK,tma_v,mV,tma_c,mC,self.cluster_layout_vmnk,self.q_smem_s,self.k_smem_s,self.v_smem_s,self.p_tmem_s,self.p_smem_s,self.c_smem_s,self.epi_tile,lse).launch(grid=(1,1,1),block=[self.threads_per_cta,1,1],stream=stream)
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@cute.kernel
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def _kernel(self, qk_mma, pv_mma, tma_q, mQ, tma_k, mK, tma_v, mV, tma_c, mC, cl_vmnk, q_smem_s, k_smem_s, v_smem_s, p_tmem_s, p_smem_s, c_smem_s, epi_tile, mLSE):
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warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())
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tidx,_,_ = cute.arch.thread_idx()
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if warp_idx == self.tma_warp_id:
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cpasync.prefetch_descriptor(tma_q); cpasync.prefetch_descriptor(tma_k); cpasync.prefetch_descriptor(tma_v); cpasync.prefetch_descriptor(tma_c)
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@cute.struct
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class SS:
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q_bar: cute.struct.MemRange[cutlass.Int64, self.q_stage*2]
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kv_bar: cute.struct.MemRange[cutlass.Int64, self.kv_stage*2]
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s_bar: cute.struct.MemRange[cutlass.Int64, 2]
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acc_bar: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage*2]
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tmem_dealloc: cutlass.Int64; holding: cutlass.Int32
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smem = utils.SmemAllocator(); st = smem.allocate(SS)
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qp,qc = pipeline.PipelineTmaUmma.create(barrier_storage=st.q_bar.data_ptr(),num_stages=self.q_stage,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,1),tx_count=self.q_tx_bytes,cta_layout_vmnk=cl_vmnk,defer_sync=True).make_participants()
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kvp,kvc = pipeline.PipelineTmaUmma.create(barrier_storage=st.kv_bar.data_ptr(),num_stages=self.kv_stage,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,1),tx_count=self.kv_tx_bytes,cta_layout_vmnk=cl_vmnk,defer_sync=True).make_participants()
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s_prod,s_cons = pipeline.PipelineUmmaAsync.create(barrier_storage=st.s_bar.data_ptr(),num_stages=1,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,32*len(self.epilogue_warp_id))).make_participants()
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softmax_done_bar = pipeline.NamedBarrier(barrier_id=3, num_threads=32 + 32*len(self.epilogue_warp_id))
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final_o_bar = pipeline.NamedBarrier(barrier_id=4, num_threads=32 + 32*len(self.epilogue_warp_id))
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acc_pipe = pipeline.PipelineUmmaAsync.create(barrier_storage=st.acc_bar.data_ptr(),num_stages=self.num_acc_stage,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,len(self.epilogue_warp_id)),cta_layout_vmnk=cl_vmnk,defer_sync=True)
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tmem_bar = pipeline.NamedBarrier(barrier_id=2,num_threads=32*len((self.mma_warp_id,*self.epilogue_warp_id)))
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tmem = utils.TmemAllocator(st.holding.ptr,barrier_for_retrieve=tmem_bar,allocator_warp_id=self.epilogue_warp_id[0],is_two_cta=cute.size(qk_mma.thr_id.shape)==2,two_cta_tmem_dealloc_mbar_ptr=st.tmem_dealloc.ptr)
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pipeline.pipeline_init_arrive(cluster_shape_mn=cl_vmnk,is_relaxed=True)
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sQ = smem.allocate_tensor(element_type=self.q_dtype,layout=q_smem_s.outer,byte_alignment=128,swizzle=q_smem_s.inner)
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sK = smem.allocate_tensor(element_type=self.q_dtype,layout=k_smem_s.outer,byte_alignment=128,swizzle=k_smem_s.inner)
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sV = smem.allocate_tensor(element_type=self.q_dtype,layout=v_smem_s.outer,byte_alignment=128,swizzle=v_smem_s.inner)
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sC = smem.allocate_tensor(element_type=self.o_dtype,layout=c_smem_s.outer,byte_alignment=128,swizzle=c_smem_s.inner)
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sP = smem.allocate_tensor(element_type=self.q_dtype,layout=p_smem_s.outer,byte_alignment=128,swizzle=p_smem_s.inner)
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gQ = cute.local_tile(mQ,cute.slice_(self.qk_mma_tiler,(None,0,None)),(None,None,None))
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gK = cute.local_tile(mK,cute.slice_(self.qk_mma_tiler,(0,None,None)),(None,None,None))
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gV = cute.local_tile(mV,cute.slice_(self.pv_mma_tiler,(0,None,None)),(None,None,None))
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gC = cute.local_tile(mC,cute.slice_(self.pv_mma_tiler,(None,None,0)),(None,None,None))
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n_kv_tiles = cute.size(gK, mode=[3])
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qk_thr = qk_mma.get_slice(0); pv_thr = pv_mma.get_slice(0)
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tCgQ = qk_thr.partition_A(gQ); tCgK = qk_thr.partition_B(gK)
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tCgV = pv_thr.partition_B(gV); tCgC = pv_thr.partition_C(gC)
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a_lay = cute.make_layout(cute.slice_(cl_vmnk,(0,0,None,0)).shape)
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tAsQ,tAgQ = cpasync.tma_partition(tma_q,0,a_lay,cute.group_modes(sQ,0,3),cute.group_modes(tCgQ,0,3))
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b_lay = cute.make_layout(cute.slice_(cl_vmnk,(0,None,0,0)).shape)
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tBsK,tBgK = cpasync.tma_partition(tma_k,0,b_lay,cute.group_modes(sK,0,3),cute.group_modes(tCgK,0,3))
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tVsV,tVgV = cpasync.tma_partition(tma_v,0,b_lay,cute.group_modes(sV,0,3),cute.group_modes(tCgV,0,3))
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tAgQ = tAgQ[(None,0,None,0)]; tBgK = tBgK[(None,0,None,0)]; tVgV = tVgV[(None,0,None,0)]
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tCrQ = qk_mma.make_fragment_A(sQ); tCrK = qk_mma.make_fragment_B(sK)
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tCrV = pv_mma.make_fragment_B(sV)
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qk_as = qk_thr.partition_shape_C(self.qk_mma_tiler[:2])
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tStS = qk_thr.make_fragment_C(qk_as)
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tStS0 = cute.make_tensor(tStS.iterator + self.tmem_s0_offset, tStS.layout)
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pv_as = pv_thr.partition_shape_C(self.pv_mma_tiler[:2])
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tOtO = pv_thr.make_fragment_C(pv_as)
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tOtO0 = cute.make_tensor(tOtO.iterator + self.tmem_o0_offset, tOtO.layout)
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# PV A-operand: define both tOrP0 (TMEM-P) and tCrP (SMEM-P) unconditionally.
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# CuTeDSL scoping: variables must be assigned unconditionally (no if/else).
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tP = cute.make_tensor(tStS.iterator, p_tmem_s.outer)
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tOrP_base = pv_thr.make_fragment_A(tP if not self.use_smem_p else sP)
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tOrP = tOrP_base[(None,None,None,0)]
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tCrP = pv_mma.make_fragment_A(sP)
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# tOrP0: PV A-operand with TMEM column offset for P0 (TMEM-P path).
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# self.tOrP0_offset is pre-computed in _setup as a Python int.
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# Use const_expr if/else for compile-time conditional.
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if const_expr(self.tOrP0_offset > 0):
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tOrP0 = cute.make_tensor(tOrP.iterator + self.tOrP0_offset, tOrP.layout)
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else:
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tOrP0 = tOrP
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tCtO_fake = pv_mma.make_fragment_C(cute.append(pv_as, self.num_acc_stage))
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pipeline.pipeline_init_wait(cluster_shape_mn=cl_vmnk)
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# ===== TMA LOAD warp =====
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if warp_idx == self.tma_warp_id:
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qp.reset(); qh = qp.acquire_and_advance()
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cute.copy(tma_q, tAgQ[(None, Int32(0))], tAsQ[(None, qh.index)], tma_bar_ptr=qh.barrier)
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qp.tail()
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kvp.reset(); pk = kvp.try_acquire()
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for kt in cutlass.range(0, self.n_kv_tiles, 1, unroll=1):
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kvh = kvp.acquire_and_advance(pk)
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cute.copy(tma_k, tBgK[(None, kt)], tBsK[(None, kvh.index)], tma_bar_ptr=kvh.barrier)
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cute.copy(tma_v, tVgV[(None, kt)], tVsV[(None, kvh.index)], tma_bar_ptr=kvh.barrier)
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pk = cutlass.Boolean(1)
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kvp.tail()
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# ===== MMA warp =====
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if warp_idx == self.mma_warp_id:
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tmem.wait_for_alloc()
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qc.reset(); qh = qc.wait_and_advance(); qh.release()
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kvc.reset(); pk = kvc.try_wait()
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acc_st = pipeline.make_pipeline_state(pipeline.PipelineUserType.Producer, self.num_acc_stage)
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acc_pipe.producer_acquire(acc_st)
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for kt in range(self.n_kv_tiles):
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kvh = kvc.wait_and_advance(pk); pk = cutlass.Boolean(1)
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sh = s_prod.acquire_and_advance()
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qk_mma.set(tcgen05.Field.ACCUMULATE, False)
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for kb in cutlass.range(cute.size(tCrQ, mode=[2]), unroll_full=True):
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cute.gemm(qk_mma, tStS0, tCrQ[(None,None,kb,0)], tCrK[(None,None,kb,kvh.index)], tStS0)
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qk_mma.set(tcgen05.Field.ACCUMULATE, True)
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cute.arch.fence_view_async_tmem_store()
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sh.commit()
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softmax_done_bar.arrive_and_wait()
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pv_mma.set(tcgen05.Field.ACCUMULATE, kt != 0)
|
|
if not self.use_smem_p:
|
|
# TMEM-P: PV reads P from TMEM
|
|
for kb in cutlass.range(cute.size(tOrP0, mode=[2]), unroll_full=True):
|
|
cute.gemm(pv_mma, tOtO0, tOrP0[(None,None,kb)], tCrV[(None,None,kb,kvh.index)], tOtO0)
|
|
pv_mma.set(tcgen05.Field.ACCUMULATE, True)
|
|
else:
|
|
# SMEM-P: PV reads P from SMEM
|
|
for kb in cutlass.range(cute.size(tCrP, mode=[2]), unroll_full=True):
|
|
cute.gemm(pv_mma, tOtO0, tCrP[(None,None,kb,0)], tCrV[(None,None,kb,kvh.index)], tOtO0)
|
|
pv_mma.set(tcgen05.Field.ACCUMULATE, True)
|
|
cute.arch.fence_view_async_tmem_store()
|
|
kvh.release()
|
|
acc_pipe.producer_commit(acc_st); acc_st.advance()
|
|
final_o_bar.arrive()
|
|
acc_pipe.producer_tail(acc_st)
|
|
|
|
# ===== SOFTMAX + CORRECTION EPILOGUE warps =====
|
|
if warp_idx < self.mma_warp_id:
|
|
tmem.allocate(self.num_tmem_alloc_cols)
|
|
tmem.wait_for_alloc()
|
|
tmem_ptr = tmem.retrieve_ptr(self.qk_acc_dtype)
|
|
sfw_idx = tidx % (32 * len(self.epilogue_warp_id))
|
|
|
|
# S load atoms
|
|
tmem_load_atom = cute.make_copy_atom(tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)), self.qk_acc_dtype)
|
|
tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tStS0)
|
|
thr_load = tiled_tmem_load.get_slice(sfw_idx)
|
|
tTMEM_LOADtS = thr_load.partition_S(tStS0)
|
|
cS = cute.make_identity_tensor((self.qk_mma_tiler[0], self.qk_mma_tiler[1]))
|
|
tScS = qk_thr.partition_C(cS)
|
|
tTMEM_LOADcS = thr_load.partition_D(tScS)
|
|
|
|
# P store atoms: TMEM-P (always defined, only used when use_smem_p=False)
|
|
p_cols_fp32 = self.pv_mma_tiler[2] * self.q_dtype.width // self.qk_acc_dtype.width
|
|
tStP_layout = cute.composition(tStS.layout, cute.make_layout((self.pv_mma_tiler[0], p_cols_fp32)))
|
|
# Use 0 as P offset when SMEM-P (these atoms are never used, but must be valid)
|
|
tStP0 = cute.make_tensor(tStS.iterator + max(self.tmem_p0_offset, 0), tStP_layout)
|
|
tmem_store_atom = cute.make_copy_atom(tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(32)), self.qk_acc_dtype)
|
|
tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tStP0)
|
|
thr_store = tiled_tmem_store.get_slice(sfw_idx)
|
|
tTMEM_STOREtP = thr_store.partition_D(tStP0)
|
|
tScP_layout = cute.composition(tScS.layout, cute.make_layout((self.pv_mma_tiler[0], p_cols_fp32)))
|
|
tScP = cute.make_tensor(tScS.iterator, tScP_layout)
|
|
tTMEM_STOREcP = thr_store.partition_S(tScP)
|
|
|
|
# P SMEM copy atoms: SMEM-P
|
|
# Strategy: Use make_cotiled_copy with atom_layout_tv built from
|
|
# the TMEM-load coordinate partition + sP address mapping.
|
|
#
|
|
# The TMEM-load partition gives each thread (m, k) coordinates via tTMEM_LOADcS.
|
|
# We compose these coordinates with sP's logical address layout to get
|
|
# (tid, vid) -> sP_addr. Then make_cotiled_copy creates a proper TiledCopy.
|
|
#
|
|
# Key: sP's outer layout maps (m, k0, k1, k2) -> sP_addr with strides (64, 1, 16, 8192).
|
|
# We need to build atom_layout_tv in sP's flat address space, not tStS's.
|
|
#
|
|
# Step 1: Build sP address mapping in the same coordinate system as tStS.
|
|
# sP is indexed as ((m, k%16), 0, ((k//16)%4, k//64)) with strides ((64,1),0,(16,8192)).
|
|
# In the P matrix's (m, k) coordinate space:
|
|
# sP_addr = 64*m + (k%16) + 16*((k//16)%4) + 8192*(k//64)
|
|
# This is representable as a CuTe layout: (128, (16, 4, 2)) -> (64, (1, 16, 8192))
|
|
_sP_nostage = sP[(None, None, None, 0)] # remove stage dim
|
|
|
|
row_max = -Float32.inf
|
|
row_sum = Float32(0.0)
|
|
scale_log2 = Float32(self.scale_softmax_log2)
|
|
|
|
# O rescale atoms (hand-constructed, using composition layout like CUTLASS correction_rescale)
|
|
corr_tile_size = 16
|
|
tOcO = pv_thr.partition_C(cS)
|
|
tOtO_i_layout = cute.composition(tOtO0.layout, cute.make_layout((128, corr_tile_size)))
|
|
tOcO_i_layout = cute.composition(tOcO.layout, cute.make_layout((128, corr_tile_size)))
|
|
tOtO_i = cute.make_tensor(tOtO0.iterator, tOtO_i_layout)
|
|
tOcO_i = cute.make_tensor(tOcO.iterator, tOcO_i_layout)
|
|
tmem_load_o_atom = cute.make_copy_atom(
|
|
tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),
|
|
self.acc_dtype,
|
|
)
|
|
tmem_store_o_atom = cute.make_copy_atom(
|
|
tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),
|
|
self.acc_dtype,
|
|
)
|
|
tiled_tmem_load_o = tcgen05.make_tmem_copy(tmem_load_o_atom, tOtO_i)
|
|
tiled_tmem_store_o = tcgen05.make_tmem_copy(tmem_store_o_atom, tOtO_i)
|
|
thr_tmem_load_o = tiled_tmem_load_o.get_slice(sfw_idx)
|
|
thr_tmem_store_o = tiled_tmem_store_o.get_slice(sfw_idx)
|
|
tTMEM_LOADtO = thr_tmem_load_o.partition_S(tOtO_i)
|
|
tTMEM_LOADcO = thr_tmem_load_o.partition_D(tOcO_i)
|
|
tTMEM_STOREtO = thr_tmem_store_o.partition_D(tOtO_i)
|
|
n_corr_tiles = self.pv_n_tile // corr_tile_size
|
|
|
|
for kt in range(self.n_kv_tiles):
|
|
si_handle = s_cons.wait_and_advance()
|
|
|
|
tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcS.shape, self.qk_acc_dtype)
|
|
cute.copy(tiled_tmem_load, tTMEM_LOADtS, tTMEM_LOADrS)
|
|
cute.arch.fence_view_async_tmem_load()
|
|
|
|
old_row_max = row_max
|
|
frg_cnt = 4
|
|
frg_tile = cute.size(tTMEM_LOADrS) // frg_cnt
|
|
tTMEM_LOADrS_frg = cute.logical_divide(tTMEM_LOADrS, cute.make_layout(frg_tile))
|
|
for j in range(frg_cnt):
|
|
for k in range(cute.size(tTMEM_LOADrS_frg, mode=[0])):
|
|
row_max = cute.arch.fmax(row_max, tTMEM_LOADrS_frg[k, j] * scale_log2)
|
|
|
|
row_max_safe = row_max
|
|
if row_max == -cutlass.Float32.inf:
|
|
row_max_safe = Float32(0.0)
|
|
|
|
acc_scale_ = old_row_max - row_max_safe
|
|
acc_scale = cute.math.exp2(acc_scale_, fastmath=True)
|
|
if old_row_max == -cutlass.Float32.inf:
|
|
acc_scale = Float32(0.0)
|
|
row_sum *= acc_scale
|
|
|
|
rP_words = cute.make_rmem_tensor(tTMEM_STOREcP.shape, self.qk_acc_dtype)
|
|
rP_bf16 = cute.make_tensor(cute.recast_ptr(rP_words.iterator, dtype=self.q_dtype), tTMEM_LOADrS.layout)
|
|
minus_row_max = Float32(0.0) - row_max_safe
|
|
|
|
rP_bf16_frg = cute.logical_divide(rP_bf16, cute.make_layout(frg_tile))
|
|
for j in range(frg_cnt):
|
|
for k in range(cute.size(tTMEM_LOADrS_frg, mode=[0])):
|
|
tTMEM_LOADrS_frg[k, j] = tTMEM_LOADrS_frg[k, j] * scale_log2 + minus_row_max
|
|
tTMEM_LOADrS_frg[k, j] = cute.math.exp2(tTMEM_LOADrS_frg[k, j], fastmath=True)
|
|
row_sum = row_sum + tTMEM_LOADrS_frg[k, j]
|
|
s_vec = tTMEM_LOADrS_frg[None, j].load()
|
|
rP_bf16_frg[None, j].store(s_vec.to(self.q_dtype))
|
|
|
|
if not self.use_smem_p:
|
|
# TMEM-P: store P to TMEM via register bridge
|
|
cute.copy(tiled_tmem_store, rP_words, tTMEM_STOREtP)
|
|
cute.arch.fence_view_async_tmem_store()
|
|
else:
|
|
# SMEM-P: write P to sP using coordinate-indexed store.
|
|
# Uses tTMEM_LOADcS identity tensor to get (m, k) coordinates.
|
|
# DEBUG: Write a known pattern to sP to verify the coordinate mapping.
|
|
# Pattern: sP[m, k] = (m + k) % 256 as BF16 (unique per position)
|
|
for j0 in range(32):
|
|
for j1 in range(4):
|
|
coord = tTMEM_LOADcS[(j0, 0), j1, 0, 0]
|
|
m_coord = coord[0]
|
|
k_coord = coord[1]
|
|
k0 = k_coord % 16
|
|
k1 = (k_coord // 16) % 4
|
|
k2 = k_coord // 64
|
|
# Debug: write (m + k) mod 256 instead of actual P value
|
|
_sP_nostage[(m_coord, k0), 0, (k1, k2)] = rP_bf16[(j0, 0), j1, 0, 0]
|
|
cute.arch.fence_proxy("async.shared", space="cta")
|
|
if kt > 0:
|
|
tTMrO = cute.make_rmem_tensor(
|
|
(tTMEM_LOADcO.shape, 128 // corr_tile_size), self.acc_dtype
|
|
)
|
|
for i in range(n_corr_tiles):
|
|
tTMrO_i_ = tTMrO[None, i]
|
|
tTMrO_i_layout = cute.composition(
|
|
tTMrO_i_.layout, cute.make_layout(tTMrO.shape[0])
|
|
)
|
|
tTMrO_i = cute.make_tensor(tTMrO_i_.iterator, tTMrO_i_layout)
|
|
tTMEM_LOADtO_i = cute.make_tensor(
|
|
tTMEM_LOADtO.iterator + i * corr_tile_size,
|
|
tTMEM_LOADtO.layout,
|
|
)
|
|
tTMEM_STOREtO_i = cute.make_tensor(
|
|
tTMEM_STOREtO.iterator + i * corr_tile_size,
|
|
tTMEM_STOREtO.layout,
|
|
)
|
|
cute.copy(tiled_tmem_load_o, tTMEM_LOADtO_i, tTMrO_i)
|
|
for k in cutlass.range(cute.size(tTMrO_i), vectorize=True):
|
|
tTMrO_i[k] = tTMrO_i[k] * acc_scale
|
|
cute.copy(tiled_tmem_store_o, tTMrO_i, tTMEM_STOREtO_i)
|
|
cute.arch.fence_view_async_tmem_store()
|
|
|
|
si_handle.release()
|
|
softmax_done_bar.arrive()
|
|
|
|
# Wait for MMA's PV[N-1] to commit before reading O.
|
|
final_o_bar.arrive_and_wait()
|
|
|
|
# ============================================================
|
|
# CORRECTION EPILOG: One-way TMEM → registers → normalize → SMEM → GMEM
|
|
# ============================================================
|
|
# Follows CUTLASS epilogue_tma_store pattern exactly:
|
|
# transform_partitioned_tensor_layout → flat_divide →
|
|
# get_tmem_load_op → make_tmem_copy → partition_S →
|
|
# get_smem_store_op → make_tiled_copy_D → partition_D →
|
|
# cpasync.tma_partition → copy loop
|
|
# Eliminates the 3% per-tile TMEM round-trip error by using
|
|
# paired atoms that preserve the C-fragment layout.
|
|
# ============================================================
|
|
|
|
# D5a: When normalize=False, still do one-way trip but skip 1/row_sum.
|
|
if const_expr(self.normalize):
|
|
inv_row_sum = Float32(1.0) / row_sum
|
|
|
|
# Step 1: Transform partitioned tensor layouts (CUTLASS pattern)
|
|
# ((ATOM_M, ATOM_N), MMA_M, MMA_N, ...) -> ((ATOM_M, MMA_M), (ATOM_N, MMA_N), ...)
|
|
tOtO_xfm = _transform_partitioned_tensor_layout(
|
|
cute.make_tensor(tmem_ptr + self.tmem_o0_offset, tOtO.layout))
|
|
tCgC_xfm = _transform_partitioned_tensor_layout(tCgC)
|
|
|
|
# Step 2: TMEM load copy (epilogue_tmem_copy_and_partition pattern)
|
|
from cutlass.utils.blackwell_helpers import get_tmem_load_op as _get_tmem_load_op
|
|
tmem_copy_atom = _get_tmem_load_op(
|
|
self.cta_tile_shape_mnk, self.c_layout, self.o_dtype, self.acc_dtype,
|
|
epi_tile, self.use_2cta_instrs,
|
|
)
|
|
# flat_divide by epi_tile to create sub-tiled views
|
|
tOtO_epi = cute.flat_divide(tOtO_xfm, epi_tile)
|
|
tCgC_epi = cute.flat_divide(tCgC_xfm, epi_tile)
|
|
# make_tmem_copy with the first sub-tile shape
|
|
tiled_copy_t2r = tcgen05.make_tmem_copy(tmem_copy_atom, tOtO_epi[(None, None, 0, 0)])
|
|
thr_t2r = tiled_copy_t2r.get_slice(sfw_idx)
|
|
# Partition source (TMEM) and destination (GMEM-derived register shape)
|
|
tTR_tAcc = thr_t2r.partition_S(tOtO_epi)
|
|
tTR_gC = thr_t2r.partition_D(tCgC_epi)
|
|
# Register tensor shape: keep (T2R, T2R_M, T2R_N) dims, zero the rest
|
|
# After partition_D, tTR_gC has (T2R, T2R_M, T2R_N, EPI_M, EPI_N, REST...)
|
|
# We slice to get just the per-subtile register count.
|
|
_tTR_gC_shape = tTR_gC.shape
|
|
_n_rest = len(_tTR_gC_shape) - 3 # 3 leading dims: T2R, T2R_M, T2R_N
|
|
tTR_rAcc = cute.make_rmem_tensor(
|
|
tTR_gC[(None, None, None) + (0,) * _n_rest].shape, self.acc_dtype)
|
|
|
|
# Step 3: SMEM store copy (epilogue_smem_copy_and_partition pattern)
|
|
smem_copy_atom = get_smem_store_op(
|
|
self.c_layout, self.o_dtype, self.acc_dtype, tiled_copy_t2r)
|
|
tiled_copy_r2s = cute.make_tiled_copy_D(smem_copy_atom, tiled_copy_t2r)
|
|
thr_r2s = tiled_copy_r2s.get_slice(sfw_idx)
|
|
tRS_sC = thr_r2s.partition_D(sC)
|
|
tTR_rC = cute.make_rmem_tensor(tRS_sC[(None, None, None, 0)].shape, self.o_dtype)
|
|
|
|
# Step 4: TMA store partition (cpasync.tma_partition for S2G)
|
|
# flat_divide tCgC for TMA partition (need the un-xfm version for tma_partition)
|
|
tCgC_epi_tma = cute.flat_divide(tCgC, epi_tile)
|
|
bSG_sC, bSG_gC = cpasync.tma_partition(
|
|
tma_c, 0, cute.make_layout(1),
|
|
cute.group_modes(sC, 0, 2),
|
|
cute.group_modes(tCgC_epi_tma, 0, 2),
|
|
)
|
|
|
|
# Step 5: Correction loop — for each sub-tile: TMEM → reg → normalize → SMEM
|
|
tTR_tAcc_g = cute.group_modes(tTR_tAcc, 3, cute.rank(tTR_tAcc))
|
|
subtile_cnt = cute.size(tTR_tAcc_g.shape, mode=[3])
|
|
|
|
for subtile_idx in range(subtile_cnt):
|
|
# Load O from TMEM (preserves C-fragment layout via paired atom)
|
|
tTR_tAcc_mn = tTR_tAcc_g[(None, None, None, subtile_idx)]
|
|
cute.copy(tiled_copy_t2r, tTR_tAcc_mn, tTR_rAcc)
|
|
|
|
# Normalize: multiply by inv_row_sum (exact in FP32)
|
|
if const_expr(self.normalize):
|
|
for j in cutlass.range(cute.size(tTR_rAcc), vectorize=True):
|
|
tTR_rAcc[j] = tTR_rAcc[j] * inv_row_sum
|
|
|
|
# Convert to output dtype and store to SMEM
|
|
acc_vec = tiled_copy_r2s.retile(tTR_rAcc).load()
|
|
acc_vec = acc_vec.to(self.o_dtype)
|
|
tTR_rC.store(acc_vec)
|
|
|
|
# Store to SMEM
|
|
c_buffer = subtile_idx % self.num_c_stage
|
|
cute.copy(tiled_copy_r2s, tTR_rC, tRS_sC[(None, None, None, c_buffer)])
|
|
|
|
# Fence and barrier
|
|
cute.arch.fence_proxy("async.shared", space="cta")
|
|
corr_epi_bar = pipeline.NamedBarrier(
|
|
barrier_id=5, num_threads=32 * len(self.epilogue_warp_id))
|
|
corr_epi_bar.arrive_and_wait()
|
|
|
|
# TMA store SMEM → GMEM
|
|
if warp_idx == self.epilogue_warp_id[0]:
|
|
# Group trailing modes and slice (CUTLASS pattern)
|
|
bSG_gC_flat = cute.group_modes(bSG_gC, 1, cute.rank(bSG_gC))
|
|
cute.copy(tma_c, bSG_sC[(None, c_buffer)], bSG_gC_flat[(None, Int32(0))])
|
|
cute.arch.cp_async_bulk_commit_group()
|
|
cute.arch.cp_async_bulk_wait_group(0, read=True)
|
|
corr_epi_bar.arrive_and_wait()
|
|
|
|
# D5a: Write LSE (log-softmax) when normalize=False
|
|
# lse = ln(row_sum) + row_max * ln(2)
|
|
# row_max is in scale_log2 domain, multiply by ln(2) to convert.
|
|
if const_expr(not self.normalize):
|
|
_row_max_safe = row_max
|
|
if row_max == -cutlass.Float32.inf:
|
|
_row_max_safe = Float32(0.0)
|
|
if sfw_idx == 0:
|
|
_ln2 = Float32(0.6931471805599453) # ln(2)
|
|
lse_val = cute.math.log(row_sum, fastmath=True) + _row_max_safe * _ln2
|
|
mLSE[0] = lse_val
|
|
|
|
tmem.relinquish_alloc_permit()
|
|
tmem.free(tmem_ptr)
|