biondizzle
97656a5cd1
Key fixes: - PipelineUmmaAsync consumer group: 32*4=128 threads (not 4 warps) - TMEM offsets computed from find_tmem_tensor_col_offset (not hardcoded) - P fragment from p_tmem_s.outer + make_fragment_A (matching fmha.py) - V SMEM aliasing via recast_ptr Status: - Stage A: cosine 0.999999 ✅ - Stage B: runs without crash, identity softmax cosine -0.02 ❌ - Diagnostics: TMEM layout inspection, bisection results
264 lines
12 KiB
Python
264 lines
12 KiB
Python
"""
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TMEM Addressing Test: verify offset computation from layouts.
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Allocates TMEM, computes offsets from QK accumulator and PV fragment sizes,
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writes known values via tcgen05.st at each offset region, reads them back
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via tcgen05.ld, and verifies correctness. No MMA, no softmax, no V load.
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This validates that our offset arithmetic is correct before wiring it into Stage B.
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"""
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import torch
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import cutlass
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import cutlass.cute as cute
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import cutlass.utils as utils
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import cutlass.pipeline as pipeline
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from cutlass.cute.nvgpu import cpasync, tcgen05
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from cutlass import Float32, BFloat16, Int32, Boolean, const_expr
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from cutlass.utils import LayoutEnum
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import cuda.bindings.driver as cuda
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class TmemAddressingTest:
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def __init__(self, mma_tiler_mn):
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self.acc_dtype = Float32
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self.qk_acc_dtype = Float32
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self.q_dtype = BFloat16
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self.o_dtype = BFloat16
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self.mma_tiler_mn = mma_tiler_mn
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self.mma_tiler = (*mma_tiler_mn, 1)
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self.cluster_shape_mn = (1, 1)
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self.cta_group = tcgen05.CtaGroup.ONE
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self.epilogue_warp_id = (0, 1, 2, 3)
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self.mma_warp_id = 4
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self.tma_warp_id = 5
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self.threads_per_cta = 192
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self.tmem_alloc_sync_bar_id = 2
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self.tmem_dealloc_sync_bar_id = 3
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self.num_c_stage = 2
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@cute.jit
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def __call__(self, debug_buf: cute.Tensor, stream: cuda.CUstream):
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self.a_dtype = BFloat16
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self.b_dtype = BFloat16
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self.a_major = cute.nvgpu.OperandMajorMode.K
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self.b_major = cute.nvgpu.OperandMajorMode.K
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self.c_layout = LayoutEnum.RowMajor
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# Create the same MMAs as Stage B to get the same fragment layouts
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qk_mma = utils.sm100.make_trivial_tiled_mma(
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self.a_dtype, self.b_dtype, self.a_major, self.b_major,
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self.qk_acc_dtype, self.cta_group, self.mma_tiler_mn,
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tcgen05.OperandSource.SMEM)
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pv_mma = utils.sm100.make_trivial_tiled_mma(
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self.a_dtype, self.b_dtype, cute.nvgpu.OperandMajorMode.K, self.b_major,
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self.qk_acc_dtype, self.cta_group, self.mma_tiler_mn,
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tcgen05.OperandSource.TMEM)
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qk_inst_k = cute.size(qk_mma.shape_mnk, mode=[2])
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self.qk_mma_tiler = (*self.mma_tiler_mn, qk_inst_k * 4)
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pv_inst_k = cute.size(pv_mma.shape_mnk, mode=[2])
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self.pv_mma_tiler = (*self.mma_tiler_mn, pv_inst_k * 4)
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self.mma_tiler = self.qk_mma_tiler
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self.cta_tile_shape_mnk = (
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self.qk_mma_tiler[0] // cute.size(qk_mma.thr_id.shape),
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self.qk_mma_tiler[1],
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self.qk_mma_tiler[2],
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)
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self.cluster_layout_vmnk = cute.tiled_divide(
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cute.make_layout((1, 1, 1)), (qk_mma.thr_id.shape,))
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# Compute TMEM fragment sizes from layouts
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qk_thr = qk_mma.get_slice(0)
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qk_acc_shape = qk_thr.partition_shape_C(self.mma_tiler[:2])
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tStS = qk_thr.make_fragment_C(qk_acc_shape)
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qk_acc_cols = cute.size(tStS.layout, mode=[1])
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pv_thr = pv_mma.get_slice(0)
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pv_acc_shape = pv_thr.partition_shape_C(self.mma_tiler[:2])
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tOtO = pv_thr.make_fragment_C(pv_acc_shape)
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pv_acc_cols = cute.size(tOtO.layout, mode=[1])
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# P operand size: tilePlikeFP32 = qk_mma_tiler[1] * q_dtype.width // 32
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tilePlikeFP32 = self.qk_mma_tiler[1] * self.q_dtype.width // 32
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# Compute offsets
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tmem_s_offset = 0
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tmem_p_offset = qk_acc_cols # P right after QK accumulator
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tmem_o_offset = qk_acc_cols + tilePlikeFP32 # O right after P
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# Total allocation
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tmem_alloc_cols = tmem_o_offset + pv_acc_cols
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# JIT-time prints — these appear during compilation
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print(f"[TMEM] qk_acc_cols = {qk_acc_cols}")
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print(f"[TMEM] tilePlikeFP32 = {tilePlikeFP32}")
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print(f"[TMEM] pv_acc_cols = {pv_acc_cols}")
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print(f"[TMEM] tmem_s_offset = {tmem_s_offset}")
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print(f"[TMEM] tmem_p_offset = {tmem_p_offset}")
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print(f"[TMEM] tmem_o_offset = {tmem_o_offset}")
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print(f"[TMEM] tmem_alloc_cols = {tmem_alloc_cols}")
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self._kernel(
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qk_mma, pv_mma, tStS, tOtO, tmem_alloc_cols,
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tmem_s_offset, tmem_p_offset, tmem_o_offset, tilePlikeFP32,
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debug_buf, self.cluster_layout_vmnk
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).launch(grid=(1, 1, 1), block=[self.threads_per_cta, 1, 1], stream=stream)
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@cute.kernel
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def _kernel(self, qk_mma, pv_mma, tStS, tOtO, tmem_alloc_cols,
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tmem_s_offset, tmem_p_offset, tmem_o_offset, tilePlikeFP32,
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debug_buf, cl_vmnk):
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warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())
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tidx, _, _ = cute.arch.thread_idx()
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use_2cta = cute.size(qk_mma.thr_id.shape) == 2
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@cute.struct
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class SS:
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tmem_dealloc: cutlass.Int64
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holding: cutlass.Int32
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smem = utils.SmemAllocator()
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st = smem.allocate(SS)
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tmem_bar = pipeline.NamedBarrier(
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barrier_id=self.tmem_alloc_sync_bar_id,
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num_threads=32 * len((self.mma_warp_id, *self.epilogue_warp_id)))
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tmem = utils.TmemAllocator(
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st.holding.ptr, barrier_for_retrieve=tmem_bar,
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allocator_warp_id=self.epilogue_warp_id[0],
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is_two_cta=use_2cta,
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two_cta_tmem_dealloc_mbar_ptr=st.tmem_dealloc.ptr)
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pipeline.pipeline_init_arrive(cluster_shape_mn=cl_vmnk, is_relaxed=True)
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pipeline.pipeline_init_wait(cluster_shape_mvnk=cl_vmnk)
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# ── MMA WARP: allocate TMEM, write test values ──
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if warp_idx == self.mma_warp_id:
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tmem.wait_for_alloc()
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tmem_ptr = tmem.retrieve_ptr(self.acc_dtype)
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# Create TMEM tensors at computed offsets
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# Scores region: write 1.0
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tStS0 = cute.make_tensor(tStS.iterator + tmem_s_offset, tStS.layout)
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# P region: write 2.0
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tStS_P_layout = cute.composition(tStS.layout, cute.make_layout((128, tilePlikeFP32)))
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tStS_P = cute.make_tensor(tStS.iterator + tmem_p_offset, tStS_P_layout)
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# Output region: write 3.0
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tOtO0 = cute.make_tensor(tOtO.iterator + tmem_o_offset, tOtO.layout)
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# Use tcgen05.st to write known values into each region
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# We'll use the store copy atom
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sfw_idx = tidx % (32 * len(self.epilogue_warp_id))
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# Store to scores region (value = 1.0)
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tmem_store_atom = cute.make_copy_atom(
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tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(32)), self.acc_dtype)
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tiled_store = tcgen05.make_tmem_copy(tmem_store_atom, tStS0)
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thr_store = tiled_store.get_slice(sfw_idx)
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tTMEM_STOREtS = thr_store.partition_D(tStS0)
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# We need a source tensor with the same shape
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tTMEM_STOREcS = thr_store.partition_S(
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cute.make_identity_tensor((self.qk_mma_tiler[0], self.qk_mma_tiler[1])))
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# Load from scores region (verify readback)
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tmem_load_atom = cute.make_copy_atom(
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tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)), self.acc_dtype)
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tiled_load = tcgen05.make_tmem_copy(tmem_load_atom, tStS0)
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thr_load = tiled_load.get_slice(sfw_idx)
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tTMEM_LOADtS = thr_load.partition_S(tStS0)
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# The MMA warp doesn't do the ld/st — the epilogue warps do.
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# For this test, just signal that TMEM is ready, epilogue will verify.
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# But actually, MMA warp CAN write to TMEM via cute.fill or direct MMA.
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# The simplest test: MMA warp issues a QK MMA with accumulate=False (known result),
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# then epilogue warps tcgen05.ld from the scores region and dump to debug_buf.
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# For now: the MMA warp just signals and the epilogue does the verification.
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# We'll write test values using tcgen05.st from epilogue warps (they have the copy atoms).
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pass
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# ── EPILOGUE WARPS: allocate TMEM, write test values, read back ──
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if warp_idx < self.mma_warp_id:
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tmem.allocate(tmem_alloc_cols)
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tmem.wait_for_alloc()
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tmem_ptr = tmem.retrieve_ptr(self.acc_dtype)
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sfw_idx = tidx % (32 * len(self.epilogue_warp_id))
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# ── Write 1.0 to scores region ──
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tStS0 = cute.make_tensor(tStS.iterator + tmem_s_offset, tStS.layout)
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tmem_store_atom = cute.make_copy_atom(
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tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(32)), self.acc_dtype)
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tiled_store_s = tcgen05.make_tmem_copy(tmem_store_atom, tStS0)
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thr_store_s = tiled_store_s.get_slice(sfw_idx)
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tTMEM_STOREtS = thr_store_s.partition_D(tStS0)
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tScS_s = qk_mma.get_slice(0).partition_C(
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cute.make_identity_tensor((self.qk_mma_tiler[0], self.qk_mma_tiler[1])))
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tTMEM_STOREcS = thr_store_s.partition_S(tScS_s)
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# Create register tensor filled with 1.0
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tTMEM_STORErS = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)
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# Fill with 1.0
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for i in cutlass.range(cute.size(tTMEM_STORErS), unroll_full=True):
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tTMEM_STORErS.store(i, cutlass.Float32(1.0))
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cute.copy(tiled_store_s, tTMEM_STORErS, tTMEM_STOREtS)
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cute.arch.fence_view_async_tmem_store()
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# ── Read back from scores region ──
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tmem_load_atom = cute.make_copy_atom(
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tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)), self.acc_dtype)
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tiled_load_s = tcgen05.make_tmem_copy(tmem_load_atom, tStS0)
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thr_load_s = tiled_load_s.get_slice(sfw_idx)
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tTMEM_LOADtS = thr_load_s.partition_S(tStS0)
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cS = cute.make_identity_tensor((self.qk_mma_tiler[0], self.qk_mma_tiler[1]))
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tScS = qk_mma.get_slice(0).partition_C(cS)
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tTMEM_LOADcS = thr_load_s.partition_D(tScS)
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tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcS.shape, self.acc_dtype)
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cute.copy(tiled_load_s, tTMEM_LOADtS, tTMEM_LOADrS)
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cute.arch.fence_view_async_tmem_load()
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# Dump one value per thread to debug_buf for verification
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# debug_buf shape: (threads_per_cta,) Float32
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# Only epilogue warps (0..3, 128 threads) write
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if tidx < 128:
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val = tTMEM_LOADrS.load()
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# Store first element of the loaded vector
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debug_buf[tidx] = val # type: ignore
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tmem.relinquish_alloc_permit()
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tmem.free(tmem_ptr)
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def test_tmem_addressing():
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device = torch.device("cuda")
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debug_buf = torch.zeros(128, dtype=torch.float32, device=device)
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import cutlass.torch as cutlass_torch
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mD = cutlass_torch.from_dlpack(debug_buf).mark_layout_dynamic(
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leading_dim=cutlass_torch.get_leading_dim(debug_buf))
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stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)
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kernel = TmemAddressingTest(mma_tiler_mn=(128, 128))
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print("Compiling TMEM addressing test...", flush=True)
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compiled = cute.compile(kernel, mD, stream)
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print("Running...", flush=True)
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compiled(mD, stream)
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torch.cuda.synchronize()
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print("Debug buffer (first 16 values):", debug_buf[:16].tolist())
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# All values should be 1.0 if addressing is correct
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nonzero = (debug_buf[:128] != 0).sum().item()
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ones = (debug_buf[:128] == 1.0).sum().item()
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print(f"Non-zero: {nonzero}/128, Ones: {ones}/128")
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if nonzero > 0:
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print("PASS: TMEM addressing works — read back non-zero values")
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else:
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print("FAIL: All zeros — TMEM addressing broken")
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if __name__ == "__main__":
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test_tmem_addressing()
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