biondizzle 4f706b55d7 Remove raw CUDA C++ fused router and DeepGEMM (MXFP4, wrong instruction) ...

DeepGEMM uses kind::mxf4.block_scale.block32 (MXFP4, UE8M0 scales, 32-elem blocks).
DSV4 uses NVF4: kind::mxf4nvf4 (E2M1 microscales, 16-elem blocks).
Using MXFP4 would require E2M1->UE8M0 conversion. NO CONVERSIONS.

Rewriting fused router in CuTeDSL with MmaMXF4NVF4Op (sf_vec_size=16).

2026-06-01 07:51:31 +00:00

..

attention

FMHA sink: don't double-scale sink bias

2026-05-31 23:12:20 +00:00

cache

fix: correct gather.py kernel_dir path

2026-05-30 21:12:09 +00:00

compressor

fix: import torch.utils.cpp_extension explicitly in production_compress

2026-06-01 05:20:44 +00:00

cuda

fix: move compressor position_bias into CUDA kernel (was Python loop)

2026-06-01 05:54:44 +00:00

gemm

NVFP4-1.1: Mark fp4_quant.py as toolchain-blocked, clean up test files

2026-05-28 04:59:01 +00:00

indexer

Wire indexer compute_index_scores_topk + fix compressor imports

2026-05-30 21:19:06 +00:00

router

Remove raw CUDA C++ fused router and DeepGEMM (MXFP4, wrong instruction)

2026-06-01 07:51:31 +00:00

__init__.py

Restructure: cutedsl/ -> dsv4/ with proper layering

2026-05-21 17:30:44 +00:00