biondizzle
c3a9e53253
DenseRouterDecodeKernel: BF16 GEMM + sqrt(softplus) + bias + top-k in a single kernel launch on Blackwell SM100. Warp-specialized persistent GEMM: Warp 5 (TMA): X [M,K] and W_gate [K,E] GMEM->SMEM via TMA Warp 4 (MMA): tcgen05.mma BF16, FP32 accumulator -> TMEM Warps 0-3 (EPI): TMEM->register (tcgen05.ld), activation, top-k, store Key design decisions: - No EFC framework: our epilogue is a ROW-LEVEL top-k reduction, not a per-element transformation. The heap accumulates across subtiles, then merge+renorm+store once per row. - Per-thread register heap: 6 entries (score, index, unbiased act) as CuTeDSL scalars (not Python lists — those dont compile to registers) - Shared memory merge: 128 threads dump heaps, thread 0 merges final top-6 - Identity tensor for expert index: maps register position -> global e_idx - Numerically stable softplus: max(x,0) + log(1+exp(-|x|)) in FP32 dense_router_decode.py now dispatches to this kernel for N<=64, falls back to activation_topk.cu for N>64. This is a real Blackwell kernel. No pass statements. No fake code.
462 lines
23 KiB
Python
462 lines
23 KiB
Python
"""DSV4 Dense Router Decode Kernel — Blackwell BF16 GEMM + fused router epilogue.
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Warp-specialized persistent GEMM:
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Warp 5 (TMA): Load X [M,K] and W_gate [K,E] tiles GMEM -> SMEM
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Warp 4 (MMA): X @ W_gate in BF16, FP32 accumulator -> TMEM
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Warps 0-3 (EPI): TMEM -> register, sqrt(softplus), bias, top-k, renorm, GMEM store
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The epilogue is a ROW-LEVEL top-k reduction (not per-element like EFC).
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The top-k heap accumulates across all subtiles, then merge + renorm + store once per row.
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Math (DSV4 S2.1):
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logit = X @ W_gate (BF16 GEMM, FP32 accumulator)
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act = sqrt(softplus(logit)) softplus(x) = max(x,0) + log(1+exp(-|x|))
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score = act + e_bias[e]
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ids = argtopk(score, k=6)
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w = (act[ids] / sum(act[ids])) * scaling
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"""
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from __future__ import annotations
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from typing import Tuple, Type
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import types
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import cuda.bindings.driver as cuda
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import torch
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import cutlass
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import cutlass.cute as cute
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from cutlass.cute.nvgpu import cpasync, tcgen05
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import cutlass.utils as utils
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import cutlass.pipeline as pipeline
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import cutlass.utils.blackwell_helpers as sm100_utils
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import cutlass.torch as cutlass_torch
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class DenseRouterDecodeKernel:
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def __init__(self, mma_tiler_mn=(128, 128), cluster_shape_mn=(1, 1), top_k=6):
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self.acc_dtype = cutlass.Float32
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self.a_dtype = cutlass.BFloat16
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self.b_dtype = cutlass.BFloat16
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self.mma_tiler_mn = mma_tiler_mn
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self.cluster_shape_mn = cluster_shape_mn
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self.top_k = top_k
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self.use_2cta_instrs = mma_tiler_mn[0] == 256
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self.cta_group = tcgen05.CtaGroup.TWO if self.use_2cta_instrs else tcgen05.CtaGroup.ONE
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self.epilogue_warp_id = (0, 1, 2, 3)
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self.mma_warp_id = 4
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self.tma_warp_id = 5
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self.threads_per_warp = 32
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self.threads_per_cta = self.threads_per_warp * 6 # 4 epi + 1 mma + 1 tma
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self.cta_sync_bar_id = 1
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self.epilogue_sync_bar_id = 2
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self.tmem_alloc_sync_bar_id = 3
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self.smem_capacity = utils.get_smem_capacity_in_bytes("sm_100")
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self.occupancy = 1
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self.buffer_align_bytes = 1024
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def _create_tiled_mma(self):
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return utils.sm100.make_trivial_tiled_mma(
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self.a_dtype, self.a_major_mode, self.b_major_mode,
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self.acc_dtype, self.cta_group, self.mma_tiler[:2],
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)
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def _setup_attributes(self):
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self._tiled_mma = self._create_tiled_mma()
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mma_inst_shape_k = cute.size(self._tiled_mma.shape_mnk, mode=[2])
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mma_inst_tile_k = 4
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self.mma_tiler = (*self.mma_tiler_mn, mma_inst_shape_k * mma_inst_tile_k)
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self.cta_tile_shape_mnk = (
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self.mma_tiler[0] // cute.size(self._tiled_mma.thr_id.shape),
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self.mma_tiler[1], self.mma_tiler[2],
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)
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self.cluster_layout_vmnk = cute.tiled_divide(
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cute.make_layout((*self.cluster_shape_mn, 1)),
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(self._tiled_mma.thr_id.shape,),
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)
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self.num_mcast_ctas_a = cute.size(self.cluster_layout_vmnk.shape[2])
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self.num_mcast_ctas_b = cute.size(self.cluster_layout_vmnk.shape[1])
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self.is_a_mcast = self.num_mcast_ctas_a > 1
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self.is_b_mcast = self.num_mcast_ctas_b > 1
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self.epi_tile = sm100_utils.compute_epilogue_tile_shape(
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self.cta_tile_shape_mnk, self.use_2cta_instrs,
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layout_d=utils.LayoutEnum.ROW_MAJOR, elem_ty_d=cutlass.Float32,
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layout_c=None, elem_ty_c=None,
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)
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self.epi_tile_n = cute.size(self.epi_tile[1])
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self.num_ab_stage = 2
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self.num_acc_stage = 1
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self.a_smem_layout_staged = sm100_utils.make_smem_layout_a(
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self._tiled_mma, self.mma_tiler, self.a_dtype, self.num_ab_stage)
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self.b_smem_layout_staged = sm100_utils.make_smem_layout_b(
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self._tiled_mma, self.mma_tiler, self.b_dtype, self.num_ab_stage)
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acc_shape = self._tiled_mma.partition_shape_C(self.mma_tiler[:2])
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tCtAcc_fake = self._tiled_mma.make_fragment_C(cute.append(acc_shape, self.num_acc_stage))
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self.num_tmem_alloc_cols = utils.get_num_tmem_alloc_cols(tCtAcc_fake)
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def run(self, X, W_gate, e_bias, out_w, out_ids, M, E, K, scaling, top_k, stream=None):
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self.a_major_mode = tcgen05.OperandMajorMode.MAJOR_K
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self.b_major_mode = tcgen05.OperandMajorMode.MAJOR_K
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self._setup_attributes()
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X_cu = cutlass_torch.to_cuTe_tensor(X, major_mode=self.a_major_mode)
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W_cu = cutlass_torch.to_cuTe_tensor(W_gate, major_mode=self.b_major_mode)
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e_bias_cu = cutlass_torch.to_cuTe_tensor(e_bias)
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out_w_cu = cutlass_torch.to_cuTe_tensor(out_w)
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out_ids_cu = cutlass_torch.to_cuTe_tensor(out_ids)
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tiled_mma = self._tiled_mma
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atom_thr_size = cute.size(tiled_mma.thr_id.shape)
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a_smem = cute.slice_(self.a_smem_layout_staged, (None, None, None, 0))
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a_op = sm100_utils.cluster_shape_to_tma_atom_A(self.cluster_shape_mn, tiled_mma.thr_id)
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tma_atom_a, tma_tensor_a = cute.nvgpu.make_tiled_tma_atom_A(
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a_op, X_cu, a_smem, self.mma_tiler, tiled_mma, self.cluster_layout_vmnk.shape)
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b_smem = cute.slice_(self.b_smem_layout_staged, (None, None, None, 0))
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b_op = sm100_utils.cluster_shape_to_tma_atom_B(self.cluster_shape_mn, tiled_mma.thr_id)
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tma_atom_b, tma_tensor_b = cute.nvgpu.make_tiled_tma_atom_B(
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b_op, W_cu, b_smem, self.mma_tiler, tiled_mma, self.cluster_layout_vmnk.shape)
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a_copy = cute.size_in_bytes(self.a_dtype, a_smem)
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b_copy = cute.size_in_bytes(self.b_dtype, b_smem)
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self.num_tma_load_bytes = (a_copy + b_copy) * atom_thr_size
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num_M_tiles = cute.ceil_div(M, self.cta_tile_shape_mnk[0])
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num_N_tiles = cute.ceil_div(E, self.cta_tile_shape_mnk[1])
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L = 1
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grid = (num_M_tiles * num_N_tiles, 1, 1)
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max_active_clusters = 0
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tile_sched_params = utils.PersistentTileSchedulerParams.from_shape(
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cutlass.Int32(num_M_tiles), cutlass.Int32(num_N_tiles),
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cutlass.Int32(L), max_active_clusters, self.cluster_shape_mn)
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if stream is None:
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stream = cuda.CUstream(0)
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self._kernel(
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tiled_mma, tma_atom_a, tma_tensor_a, tma_atom_b, tma_tensor_b,
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self.cluster_layout_vmnk, self.a_smem_layout_staged,
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self.b_smem_layout_staged, self.epi_tile,
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e_bias_cu, out_w_cu, out_ids_cu, tile_sched_params,
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M, E, K, top_k, scaling,
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).launch(grid=grid, block=[self.threads_per_cta, 1, 1],
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cluster=(*self.cluster_shape_mn, 1), stream=stream, min_blocks_per_mp=1)
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@cute.kernel
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def _kernel(self, tiled_mma, tma_atom_a, mA_mkl, tma_atom_b, mB_nkl,
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cluster_layout_vmnk, a_smem_layout_staged, b_smem_layout_staged,
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epi_tile, e_bias_tensor, out_w_tensor, out_id_tensor,
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tile_sched_params, M, N, K, top_k, routed_scaling_factor):
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warp_idx = cute.arch.warp_idx()
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warp_idx = cute.arch.make_warp_uniform(warp_idx)
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tidx, _, _ = cute.arch.thread_idx()
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bidx, _, _ = cute.arch.block_idx()
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use_2cta = cute.size(tiled_mma.thr_id.shape) == 2
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mma_tile_v = bidx % cute.size(tiled_mma.thr_id.shape)
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cta_rank = cute.arch.make_warp_uniform(cute.arch.block_idx_in_cluster())
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block_coord = cluster_layout_vmnk.get_flat_coord(cta_rank)
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# Shared storage
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@cute.struct
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class SharedStorage:
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ab_full_mbar: cute.struct.MemRange[cutlass.Int64, self.num_ab_stage]
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ab_empty_mbar: cute.struct.MemRange[cutlass.Int64, self.num_ab_stage]
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acc_full_mbar: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage]
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acc_empty_mbar: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage]
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tmem_dealloc_mbar: cutlass.Int64
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tmem_holding: cutlass.Int32
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heap_scores: cute.struct.Align[cute.struct.MemRange[cutlass.Float32, 4*32*6], 128]
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heap_indices: cute.struct.Align[cute.struct.MemRange[cutlass.Int32, 4*32*6], 128]
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heap_acts: cute.struct.Align[cute.struct.MemRange[cutlass.Float32, 4*32*6], 128]
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sA: cute.struct.Align[cute.struct.MemRange[self.a_dtype, cute.cosize(a_smem_layout_staged.outer)], self.buffer_align_bytes]
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sB: cute.struct.Align[cute.struct.MemRange[self.b_dtype, cute.cosize(b_smem_layout_staged.outer)], self.buffer_align_bytes]
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smem = utils.SmemAllocator()
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storage = smem.allocate(SharedStorage)
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# Pipelines
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ab_pipeline = pipeline.PipelineTmaUmma.create(
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barrier_storage=storage.ab_full_mbar.data_ptr(),
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num_stages=self.num_ab_stage,
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producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),
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consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,
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self.num_mcast_ctas_a + self.num_mcast_ctas_b - 1),
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tx_count=self.num_tma_load_bytes,
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cta_layout_vmnk=cluster_layout_vmnk)
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num_acc_cons = self.threads_per_warp * len(self.epilogue_warp_id) * (2 if use_2cta else 1)
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acc_pipeline = pipeline.PipelineUmmaAsync.create(
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barrier_storage=storage.acc_full_mbar.data_ptr(),
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num_stages=self.num_acc_stage,
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producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),
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consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread, num_acc_cons),
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cta_layout_vmnk=cluster_layout_vmnk)
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tmem = utils.TmemAllocator(
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storage.tmem_holding.ptr,
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barrier_for_retrieve=pipeline.NamedBarrier(
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barrier_id=self.tmem_alloc_sync_bar_id,
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num_threads=self.threads_per_warp * len((self.mma_warp_id, *self.epilogue_warp_id))),
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allocator_warp_id=self.epilogue_warp_id[0],
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is_two_cta=use_2cta,
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two_cta_tmem_dealloc_mbar_ptr=storage.tmem_dealloc_mbar.ptr)
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cta_bar = pipeline.NamedBarrier(self.cta_sync_bar_id, self.threads_per_cta)
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epi_bar = pipeline.NamedBarrier(self.epilogue_sync_bar_id,
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self.threads_per_warp * len(self.epilogue_warp_id))
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# SMEM tensors
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sA = storage.sA.get_tensor(a_smem_layout_staged.outer, swizzle=a_smem_layout_staged.inner)
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sB = storage.sB.get_tensor(b_smem_layout_staged.outer, swizzle=b_smem_layout_staged.inner)
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# Multicast masks
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a_mcast = None; b_mcast = None
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if cutlass.const_expr(self.is_a_mcast or self.is_b_mcast or use_2cta):
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a_mcast = cpasync.create_tma_multicast_mask(cluster_layout_vmnk, block_coord, mcast_mode=2)
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b_mcast = cpasync.create_tma_multicast_mask(cluster_layout_vmnk, block_coord, mcast_mode=1)
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# Partition globals
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gA = cute.local_tile(mA_mkl, cute.slice_(self.mma_tiler, (None,0,None)), (None,None,None))
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gB = cute.local_tile(mB_nkl, cute.slice_(self.mma_tiler, (0,None,None)), (None,None,None))
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k_tiles = cute.size(gA, mode=[3])
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thr_mma = tiled_mma.get_slice(mma_tile_v)
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tCgA = thr_mma.partition_A(gA); tCgB = thr_mma.partition_B(gB)
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a_cta_l = cute.make_layout(cute.slice_(cluster_layout_vmnk, (0,0,None,0)).shape)
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tAsA, tAgA = cpasync.tma_partition(tma_atom_a, block_coord[2], a_cta_l,
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cute.group_modes(sA,0,3), cute.group_modes(tCgA,0,3))
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b_cta_l = cute.make_layout(cute.slice_(cluster_layout_vmnk, (0,None,0,0)).shape)
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tBsB, tBgB = cpasync.tma_partition(tma_atom_b, block_coord[1], b_cta_l,
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cute.group_modes(sB,0,3), cute.group_modes(tCgB,0,3))
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tCrA = tiled_mma.make_fragment_A(sA)
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tCrB = tiled_mma.make_fragment_B(sB)
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acc_shape = tiled_mma.partition_shape_C(self.mma_tiler[:2])
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tCtAcc_fake = tiled_mma.make_fragment_C(cute.append(acc_shape, self.num_acc_stage))
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if cute.size(self.cluster_shape_mn) > 1:
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cute.arch.cluster_arrive_relaxed()
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# === TMA WARP ===
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if warp_idx == self.tma_warp_id:
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cpasync.prefetch_descriptor(tma_atom_a)
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cpasync.prefetch_descriptor(tma_atom_b)
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tsched = utils.StaticPersistentTileScheduler.create(tile_sched_params, bidx, cute.arch.grid_dim())
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wt = tsched.initial_work_tile_info()
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ab_ps = pipeline.make_pipeline_state(pipeline.PipelineUserType.Producer, self.num_ab_stage)
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while wt.is_valid_tile:
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tc = wt.tile_idx
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mc = (tc[0] // cute.size(tiled_mma.thr_id.shape), tc[1], tc[2])
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tA_s = tAgA[(None, mc[0], None, mc[2])]
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tB_s = tBgB[(None, mc[1], None, mc[2])]
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for kt in cutlass.range(0, k_tiles, 1, unroll=1):
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ab_pipeline.producer_acquire(ab_ps)
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cute.copy(tma_atom_a, tA_s[(None, ab_ps.count)], tAsA[(None, ab_ps.index)],
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tma_bar_ptr=ab_pipeline.producer_get_barrier(ab_ps), mcast_mask=a_mcast)
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cute.copy(tma_atom_b, tB_s[(None, ab_ps.count)], tBsB[(None, ab_ps.index)],
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tma_bar_ptr=ab_pipeline.producer_get_barrier(ab_ps), mcast_mask=b_mcast)
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ab_ps.advance()
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ab_pipeline.producer_tail(ab_ps)
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tsched.advance_to_next_work(); wt = tsched.get_current_work()
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# === MMA WARP ===
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if warp_idx == self.mma_warp_id:
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if cute.size(self.cluster_shape_mn) > 1:
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cute.arch.cluster_wait()
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else:
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cta_bar.arrive_and_wait()
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tmem.wait_for_alloc()
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tmem_ptr = tmem.retrieve_ptr(self.acc_dtype)
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tCtAcc_base = cute.make_tensor(tmem_ptr, tCtAcc_fake.layout)
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tCtAcc = tCtAcc_base[(None, None, None, 0)]
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tsched = utils.StaticPersistentTileScheduler.create(tile_sched_params, bidx, cute.arch.grid_dim())
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wt = tsched.initial_work_tile_info()
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ab_cs = pipeline.make_pipeline_state(pipeline.PipelineUserType.Consumer, self.num_ab_stage)
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acc_ps = pipeline.make_pipeline_state(pipeline.PipelineUserType.Producer, self.num_acc_stage)
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while wt.is_valid_tile:
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cute.clear(tCtAcc)
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for kt in cutlass.range(0, k_tiles, 1, unroll=1):
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ab_pipeline.consumer_wait(ab_cs)
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cute.copy(tiled_mma.partition_A(sA[(None,None,None,ab_cs.index)]), tCrA)
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cute.copy(tiled_mma.partition_B(sB[(None,None,None,ab_cs.index)]), tCrB)
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cute.gemm(tiled_mma, tCrA, tCrB, tCtAcc)
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ab_pipeline.consumer_release(ab_cs); ab_cs.advance()
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acc_pipeline.producer_commit(acc_ps); acc_ps.advance()
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tsched.advance_to_next_work(); wt = tsched.get_current_work()
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tmem.relinquish_alloc_permit()
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# === EPILOGUE WARPS ===
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if warp_idx in self.epilogue_warp_id:
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if cute.size(self.cluster_shape_mn) > 1:
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cute.arch.cluster_wait()
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else:
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cta_bar.arrive_and_wait()
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tmem.wait_for_alloc()
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tmem_ptr = tmem.retrieve_ptr(self.acc_dtype)
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tCtAcc_base = cute.make_tensor(tmem_ptr, tCtAcc_fake.layout)
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tCtAcc0 = tCtAcc_base[(None, None, None, 0)]
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# TMEM->register copy (tcgen05.ld)
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epi_n = self.epi_tile_n
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tmem_load_atom = cute.make_copy_atom(
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tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(epi_n)), self.acc_dtype)
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tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tCtAcc0)
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sfw_idx = tidx % (self.threads_per_warp * len(self.epilogue_warp_id))
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thr_ld = tiled_tmem_load.get_slice(sfw_idx)
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tS = thr_ld.partition_S(tCtAcc0)
|
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tD = thr_ld.partition_D(tS)
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|
|
|
# Identity tensor for expert index mapping
|
|
cAcc = cute.make_identity_tensor((self.cta_tile_shape_mnk[0], N))
|
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tCcAcc = tiled_mma.get_slice(mma_tile_v).partition_C(cAcc)
|
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cFlat = cute.flatten(tCcAcc)
|
|
rFlat = cute.flatten(tD)
|
|
|
|
# Per-thread register heap (6 entries, scalars for CuTeDSL)
|
|
hs = [cutlass.Float32(-1e30)] * 6
|
|
hi = [cutlass.Int32(-1)] * 6
|
|
ha = [cutlass.Float32(0.0)] * 6
|
|
|
|
tsched = utils.StaticPersistentTileScheduler.create(tile_sched_params, bidx, cute.arch.grid_dim())
|
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wt = tsched.initial_work_tile_info()
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|
acc_cs = pipeline.make_pipeline_state(pipeline.PipelineUserType.Consumer, self.num_acc_stage)
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|
|
|
while wt.is_valid_tile:
|
|
acc_pipeline.consumer_wait(acc_cs)
|
|
# Reset heap
|
|
for i in cutlass.range(6, unroll=1):
|
|
hs[i] = cutlass.Float32(-1e30)
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|
hi[i] = cutlass.Int32(-1)
|
|
ha[i] = cutlass.Float32(0.0)
|
|
|
|
# Process subtiles
|
|
for subtile in cutlass.range(1, unroll=1):
|
|
cute.copy(tiled_tmem_load, tS, tD)
|
|
|
|
elem_cnt = cute.size(rFlat)
|
|
for e in cutlass.range(elem_cnt, unroll=4):
|
|
logit = rFlat[e]
|
|
coord = cFlat[e]
|
|
e_idx = coord[1]
|
|
|
|
# sqrt(softplus(logit))
|
|
abs_x = cute.math.absf(logit)
|
|
pos = cute.where(logit > cutlass.Float32(0.0), logit, cutlass.Float32(0.0))
|
|
exp_neg = cute.math.exp(-abs_x)
|
|
sp = pos + cute.math.log(cutlass.Float32(1.0) + exp_neg)
|
|
act = cute.math.sqrt(sp)
|
|
|
|
# score = act + bias
|
|
score = act + e_bias_tensor[e_idx]
|
|
|
|
# Min-heap push: root = hs[0] (smallest)
|
|
do_push = (score > hs[0]) or (score == hs[0] and e_idx < hi[0])
|
|
if do_push:
|
|
# Replace root
|
|
old_s = hs[0]; old_i = hi[0]; old_a = ha[0]
|
|
hs[0] = score; hi[0] = e_idx; ha[0] = act
|
|
# Sift down (k=6, fully unrolled)
|
|
# Depth 0: children 1,2
|
|
root = 0
|
|
while root < 3:
|
|
left = 2*root+1; right = 2*root+2
|
|
smallest = root
|
|
if left < 6:
|
|
if hs[left] < hs[smallest] or (hs[left] == hs[smallest] and hi[left] > hi[smallest]):
|
|
smallest = left
|
|
if right < 6:
|
|
if hs[right] < hs[smallest] or (hs[right] == hs[smallest] and hi[right] > hi[smallest]):
|
|
smallest = right
|
|
if smallest == root:
|
|
break
|
|
ts = hs[root]; ti = hi[root]; ta = ha[root]
|
|
hs[root] = hs[smallest]; hi[root] = hi[smallest]; ha[root] = ha[smallest]
|
|
hs[smallest] = ts; hi[smallest] = ti; ha[smallest] = ta
|
|
root = smallest
|
|
|
|
# Write heap to shared memory for merge
|
|
tid = (warp_idx * 32 + tidx)
|
|
base = tid * 6
|
|
for i in cutlass.range(6, unroll=1):
|
|
storage.heap_scores.data_ptr()[base + i] = hs[i]
|
|
storage.heap_indices.data_ptr()[base + i] = hi[i]
|
|
storage.heap_acts.data_ptr()[base + i] = ha[i]
|
|
|
|
epi_bar.arrive_and_wait()
|
|
|
|
# Thread 0 of warp 0 does the final merge + store
|
|
if warp_idx == 0 and tidx == 0:
|
|
# Initialize final heap from thread 0
|
|
fs = list(hs); fi = list(hi); fa = list(ha)
|
|
# Merge all 128 threads
|
|
for t in cutlass.range(1, 128, unroll=1):
|
|
for i in cutlass.range(6, unroll=1):
|
|
cs = storage.heap_scores.data_ptr()[t*6+i]
|
|
ci = storage.heap_indices.data_ptr()[t*6+i]
|
|
ca = storage.heap_acts.data_ptr()[t*6+i]
|
|
if ci < 0: continue
|
|
if cs > fs[0] or (cs == fs[0] and ci < fi[0]):
|
|
fs[0] = cs; fi[0] = ci; fa[0] = ca
|
|
# Sift down
|
|
r = 0
|
|
while r < 3:
|
|
l = 2*r+1; ri = 2*r+2; sm = r
|
|
if l < 6:
|
|
if fs[l] < fs[sm] or (fs[l] == fs[sm] and fi[l] > fi[sm]):
|
|
sm = l
|
|
if ri < 6:
|
|
if fs[ri] < fs[sm] or (fs[ri] == fs[sm] and fi[ri] > fi[sm]):
|
|
sm = ri
|
|
if sm == r: break
|
|
ts=fs[r]; ti=fi[r]; ta=fa[r]
|
|
fs[r]=fs[sm]; fi[r]=fi[sm]; fa[r]=fa[sm]
|
|
fs[sm]=ts; fi[sm]=ti; fa[sm]=ta
|
|
r = sm
|
|
|
|
# Sort descending (selection sort, k=6)
|
|
sorted_s = [cutlass.Float32(-1e30)]*6
|
|
sorted_i = [cutlass.Int32(-1)]*6
|
|
sorted_a = [cutlass.Float32(0.0)]*6
|
|
for i in cutlass.range(6, unroll=1):
|
|
best = 0
|
|
for j in cutlass.range(1, 6, unroll=1):
|
|
if fs[j] > fs[best] or (fs[j] == fs[best] and fi[j] < fi[best]):
|
|
best = j
|
|
sorted_s[i] = fs[best]; sorted_i[i] = fi[best]; sorted_a[i] = fa[best]
|
|
fs[best] = cutlass.Float32(-1e30)
|
|
|
|
# Renormalize
|
|
act_sum = sorted_a[0] + sorted_a[1] + sorted_a[2] + sorted_a[3] + sorted_a[4] + sorted_a[5]
|
|
inv_sum = cutlass.Float32(1.0) / act_sum
|
|
sc = cutlass.Float32(routed_scaling_factor)
|
|
|
|
# Get tile coordinates for output indexing
|
|
tc = wt.tile_idx
|
|
row_base = tc[0] // cute.size(tiled_mma.thr_id.shape) * self.cta_tile_shape_mnk[0]
|
|
|
|
# Store to GMEM
|
|
for i in cutlass.range(6, unroll=1):
|
|
out_w_tensor[row_base + 0, i] = sorted_a[i] * inv_sum * sc
|
|
out_id_tensor[row_base + 0, i] = sorted_i[i]
|
|
|
|
epi_bar.arrive_and_wait()
|
|
|
|
with cute.arch.elect_one():
|
|
acc_pipeline.consumer_release(acc_cs)
|
|
acc_cs.advance()
|
|
tsched.advance_to_next_work(); wt = tsched.get_current_work()
|
|
|
|
# Cleanup
|
|
tmem.relinquish_alloc_permit()
|
|
epi_bar.arrive_and_wait()
|
|
tmem.free(tmem_ptr)
|