biondizzle 059c2e6cd9 D1: P store as BF16 using PV A-fragment layout ...

- Changed P store from FP32 QK C-fragment layout to BF16 PV A-fragment layout
- rP_bf16_reg stores directly to TMEM using tOrP0 layout
- Ensures softmax writes P to same TMEM columns that PV GEMM reads

2026-05-23 03:38:24 +00:00

..

attention

D1: P store as BF16 using PV A-fragment layout

2026-05-23 03:38:24 +00:00

cache

KV Cache: schema, allocator, pools, manager, append_swa kernel

2026-05-22 00:08:38 +00:00

compressor

Restructure: cutedsl/ -> dsv4/ with proper layering

2026-05-21 17:30:44 +00:00

cuda

Fix indexer score kernel: use static shared memory, correct FP4 head offsets

2026-05-22 01:45:05 +00:00

decode

Restructure: cutedsl/ -> dsv4/ with proper layering

2026-05-21 17:30:44 +00:00

gemm

Restructure: cutedsl/ -> dsv4/ with proper layering

2026-05-21 17:30:44 +00:00

indexer

Indexer: score+topk kernel, gather KV, compute_valid_lens

2026-05-22 01:20:39 +00:00

router

Router: Blackwell-native fused decode kernel — real CuTeDSL implementation

2026-05-21 22:04:20 +00:00

__init__.py

Restructure: cutedsl/ -> dsv4/ with proper layering

2026-05-21 17:30:44 +00:00