/**
 * Generalized FMHA for HD=16/64/128/256 using N=16 PV sub-tiles.
 * 
 * Key design: PV MMA uses N=16 sub-tiles to avoid the Layout D N≠16,128 bug.
 * For HD values: n_n_subtiles = HD/16 PV calls per K-tile.
 * Each sub-tile writes 16 TMEM columns starting at offset n*16.
 * 
 * Pipeline: QK(SS, N=128) → softmax → PV(SS, N=16, sub-tiled) → epilogue
 */

#include <cuda_runtime.h>
#include <cstdio>
#include <cmath>
#include <cstdlib>
#include <cstring>

#include "dsv4/kernels/attention/fmha_common.cuh"
#include "dsv4/kernels/attention/fmha_umma_desc.cuh"

using namespace dsv4::kernels::attention;

static bf16_t f32_to_bf16_host(float f) { uint32_t u; memcpy(&u,&f,4); return (uint16_t)(u>>16); }
static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; memcpy(&f,&u,4); return f; }

constexpr int SK = 128, BLOCK_MN = 128;
constexpr int NKT_QK = HD_VAL / MMA_K_BF16;
constexpr int NKT_PV = SK / MMA_K_BF16;  // 8
constexpr int TILE_SZ = BLOCK_MN * MMA_K_BF16;  // 2048 BF16
constexpr int N_NSUB = HD_VAL / 16;  // Number of N=16 sub-tiles for PV
constexpr int V_SUB_SZ = 256;  // (16,16) canonical BF16

__global__ void __launch_bounds__(128)
fmha_kernel(const bf16_t* q, const bf16_t* k, const bf16_t* v,
            bf16_t* o_out, float* o_scalar, float scale)
{
    const int tid = threadIdx.x, wid = tid / 32, lane = tid % 32;

    extern __shared__ char sbuf[];
    uint32_t* sTmemBase = (uint32_t*)sbuf;
    bf16_t* sQ0 = (bf16_t*)(((uintptr_t)(sbuf + 4) + 15) & ~(uintptr_t)15);
    bf16_t* sK0 = sQ0 + NKT_QK * TILE_SZ;
    bf16_t* sPk = (bf16_t*)(((uintptr_t)(sK0 + NKT_QK * TILE_SZ) + 127) & ~(uintptr_t)127);
    bf16_t* sV = (bf16_t*)(((uintptr_t)(sPk + TILE_SZ) + 127) & ~(uintptr_t)127);
    float* s_p_vals = (float*)(sV + V_SUB_SZ);

    // Load Q K-tiles
    for (int kt = 0; kt < NKT_QK; kt++) {
        bf16_t* sq = sQ0 + kt * TILE_SZ;
        for (int i = tid; i < TILE_SZ; i += 128) sq[i] = 0;
        for (int d = tid; d < MMA_K_BF16; d += 128) {
            int ck = d / 8, lc = d % 8;
            sq[ck * 16 * 64 + lc] = q[kt * MMA_K_BF16 + d];
        }
    }

    // Load K K-tiles
    for (int kt = 0; kt < NKT_QK; kt++) {
        bf16_t* sk = sK0 + kt * TILE_SZ;
        for (int i = tid; i < TILE_SZ; i += 128) sk[i] = 0;
        for (int r = 0; r < SK; r++) {
            for (int d = tid; d < MMA_K_BF16; d += 128) {
                int ck = d / 8, lc = d % 8;
                int tmn = r / 8, lr = r % 8;
                sk[ck * 16 * 64 + tmn * 64 + lr * 8 + lc] = k[r * HD_VAL + kt * MMA_K_BF16 + d];
            }
        }
    }

    __syncthreads();

    // TMEM alloc: need max(128, HD) columns for QK + PV output
    constexpr int TMEM_N = 128;  // Always 128 (enough for QK N=128 and PV up to HD=128)
    if (wid == 1) tmem_alloc(__cvta_generic_to_shared(sTmemBase), TMEM_N);
    __syncthreads();
    uint32_t tb = *sTmemBase;

    // ===== QK GEMM (N=128, proven working) =====
    {
        uint32_t idesc = make_idesc(BLOCK_MN, BLOCK_MN);
        for (int kt = 0; kt < NKT_QK; kt++) {
            bf16_t* sq = sQ0 + kt * TILE_SZ;
            bf16_t* sk = sK0 + kt * TILE_SZ;
            uint64_t dq = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sq), BLOCK_MN);
            uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sk), BLOCK_MN);
            if (tid == 0) umma_ss_f16(tb, dq, dk, idesc, kt > 0);
            asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
            __syncthreads();
        }
    }

    // ===== Softmax (row 0 only for T=1 decode) =====
    if (wid == 0) {
        float s_vals[SK], row_max = -INFINITY;
        for (int n = 0; n < SK / 8; n++) {
            float tmp[8];
            asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
                : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
                  "=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
                : "r"(tb + n*8));
            asm volatile("tcgen05.wait::ld.sync.aligned;");
            if (lane == 0) for (int c=0;c<8;c++) {
                s_vals[n*8+c] = tmp[c] * scale;
                row_max = fmaxf(row_max, tmp[c] * scale);
            }
        }
        row_max = wmax(row_max);
        float row_sum = 0.0f;
        if (lane == 0) for (int j=0;j<SK;j++) {
            s_vals[j] = expf(s_vals[j] - row_max);
            row_sum += s_vals[j];
        }
        row_sum = wsum(row_sum);
        if (lane == 0) for (int j=0;j<SK;j++) s_vals[j] /= row_sum;
        if (lane == 0) for (int j=0;j<SK;j++) s_p_vals[j] = s_vals[j];
    }
    __syncthreads();

    // ===== PV GEMM: N=16 sub-tiles =====
    {
        uint32_t idesc_pv16 = make_idesc(BLOCK_MN, 16);
        uint64_t dp = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sPk), BLOCK_MN);

        for (int n = 0; n < N_NSUB; n++) {
            int d_base = n * 16;
            for (int kt = 0; kt < NKT_PV; kt++) {
                // Fill sPk
                for (int i = tid; i < TILE_SZ; i += 128) sPk[i] = 0;
                if (tid < 16) {
                    int c = tid;
                    int ck = c / 8, lc = c % 8;
                    sPk[ck * 16 * 64 + 0 * 64 + 0 * 8 + lc] = f32_to_bf16(s_p_vals[kt * MMA_K_BF16 + c]);
                }

                // Load V sub-tile: (16,16) canonical for V[d_base+dd, kt*16+lr]
                for (int i = tid; i < V_SUB_SZ; i += 128) sV[i] = 0;
                for (int dd = tid; dd < 16; dd += 128) {
                    for (int lr = 0; lr < MMA_K_BF16; lr++) {
                        int r = kt * MMA_K_BF16 + lr;
                        int g_mn = dd / 8, g_k = lr / 8;
                        int llr = dd % 8, lc = lr % 8;
                        sV[g_k * 2 * 64 + g_mn * 64 + llr * 8 + lc] = v[(d_base + dd) * SK + r];
                    }
                }
                __syncthreads();

                uint64_t dv = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sV), 16);
                if (tid == 0) umma_ss_f16(tb + n * 16, dp, dv, idesc_pv16, kt > 0);
                asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
                __syncthreads();
            }
        }
    }

    // ===== Epilogue =====
    if (wid == 0) {
        float o_vals[HD_VAL];
        for (int n = 0; n < HD_VAL / 8; n++) {
            float tmp[8];
            asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
                : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
                  "=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
                : "r"(tb + n*8));
            asm volatile("tcgen05.wait::ld.sync.aligned;");
            if (lane == 0) for (int c=0;c<8;c++) o_vals[n*8+c] = tmp[c];
        }
        if (lane == 0) for (int d=0;d<HD_VAL;d++) o_out[d] = f32_to_bf16(o_vals[d]);
    }
    __syncthreads();

    // Scalar reference
    if (tid == 0) {
        float s[SK];
        for (int j=0;j<SK;j++) {
            float dot = 0.0f;
            for (int d=0;d<HD_VAL;d++) dot += bf16_to_f32(q[d]) * bf16_to_f32(k[j*HD_VAL+d]);
            s[j] = dot * scale;
        }
        float mx = -INFINITY;
        for (int j=0;j<SK;j++) mx = fmaxf(mx, s[j]);
        float sm = 0.0f;
        for (int j=0;j<SK;j++) { s[j] = expf(s[j]-mx); sm += s[j]; }
        for (int j=0;j<SK;j++) s[j] /= sm;
        for (int d=0;d<HD_VAL;d++) {
            float ov = 0.0f;
            for (int j=0;j<SK;j++) ov += s[j] * bf16_to_f32(v[d*SK+j]);
            o_scalar[d] = ov;
        }
    }

    if (wid == 0) tmem_dealloc(tb, TMEM_N);
}