d9f3fcd71d
D1.3: Fix cotiled diagnostic - use proper MMA construction
2026-05-24 00:06:50 +00:00
63e3ed0fed
D1.3: Add make_cotiled_copy diagnostic test
2026-05-24 00:05:48 +00:00
d4659d661d
shit left dangling
2026-05-23 23:58:57 +00:00
68df389c93
D1.3: Add SMEM-P coordinate diagnostic test
2026-05-23 23:23:05 +00:00
7771e5a72b
D1.3: Enhanced diagnostic - test QK C-fragment as source for make_tiled_copy_C
2026-05-23 22:24:15 +00:00
4c71998851
D1.3: Skip fragment creation in diagnostic, just print layouts
2026-05-23 22:21:31 +00:00
077ecc5a62
D1.3: Fix diagnostic - use dummy ptr 0 for shape analysis
2026-05-23 22:20:16 +00:00
7dad292401
D1.3: Fix sP allocation - p_smem_s.outer is already a layout
2026-05-23 22:19:11 +00:00
ff0b4de5e8
D1.3: Fix layout diagnostic - compute c_major outside kernel
2026-05-23 22:17:54 +00:00
999c46268b
D1.3: Layout diagnostic v2 - run inside JIT-compiled kernel
2026-05-23 22:16:57 +00:00
bbec77c1b3
D1.3: Fix layout diagnostic - remove JIT-dependent code
2026-05-23 22:15:47 +00:00
5f2343fa49
D1.3: Layout diagnostic - print all QK C-fragment and PV A-operand shapes
2026-05-23 22:14:35 +00:00
df6a2a03cb
D5b: Fix reference computation - use logsumexp for stable LSE, fix o_unnorm definition
2026-05-23 21:43:04 +00:00
3891f00b9a
D5b: Use normalized O + LSE for merge (correct formula), always output LSE
2026-05-23 21:35:40 +00:00
34125fa61c
D5b: Clean up merge test - stable formula for both ref and kernel
2026-05-23 21:33:45 +00:00
2c5799c8d8
D5b: Use reference per-row LSE for proper O normalization
2026-05-23 21:31:52 +00:00
0a0877c9bc
D5b: Fix kernel_obj reference
2026-05-23 21:30:59 +00:00
369d677c2c
D5b: Fix syntax error
2026-05-23 21:30:00 +00:00
6a47015e85
D5b: Debug reference formula mismatch, add numerically stable merge
2026-05-23 21:19:25 +00:00
023217e7b2
D5b: Python SWA+sink merge test
...
- Run FMHA twice (compressed KV + SWA KV, normalize=False)
- Merge with sink weights in Python
- Verify end-to-end correctness vs FP32 reference
2026-05-23 21:18:06 +00:00
cb9ebf33fa
D5a: Add normalize flag + LSE output
...
- normalize=True (default): O = softmax(P) @ V (existing behavior)
- normalize=False: O = P @ V (un-normalized) + lse = log(row_sum) + row_max
- LSE tensor passed as optional parameter
- Test includes D5a normalize=False verification with LSE comparison
- Cleaned up SMEM-P debug prints and broken make_tiled_copy_C code
- hd=64 TMEM-P regression: cos 0.973 PASS
2026-05-23 21:10:40 +00:00
3b98007093
diag: add 2-CTA check + fix LayoutEnum in MMA test
2026-05-23 08:45:26 +00:00
eca84bdcb5
fix: remove bad import in NVFP4 diag
2026-05-23 08:44:37 +00:00
cca62743df
fix: use quantize_activation_nvfp4 in diag
2026-05-23 08:39:12 +00:00
96a43b60f3
fix: use correct API for NVFP4-0 diag (sf_vec_size + mma_tiler_mn)
2026-05-23 08:38:19 +00:00
2b86aca551
fix: use Sm100BlockScaledPersistentDenseGemmKernel in diag
2026-05-23 08:30:43 +00:00
e87ec6c07a
fix: use randint+view for FP4/FP8 tensors in diag
2026-05-23 08:29:16 +00:00
44a917b277
fix: NVFP4-0 diag script — import SF_VEC_SIZE from quantize.py
2026-05-23 08:28:13 +00:00
c0c671e334
diag: NVFP4-0 primitive verification script
2026-05-23 08:26:56 +00:00
49d29aa1d2
D1.2: fix probe for hd=512 (MMA max N=256, use pv_n_tile)
2026-05-23 06:41:42 +00:00
5b93a41250
D1.2: simplify TMEM budget probe, fix printf args
2026-05-23 06:40:55 +00:00
d5273b7f4f
fix: cuda.CUstream import
2026-05-23 06:40:05 +00:00
39311133d6
D1.2: TMEM budget probe using @cute.jit for MLIR context
2026-05-23 06:39:27 +00:00
25a08f5de2
fix: remove unused v_fmha_layout from probe
2026-05-23 06:38:08 +00:00
de277f08ac
D1.2: TMEM budget probe with real tensor major modes
2026-05-23 06:37:34 +00:00
7af31d46be
fix: OperandMajorMode.MN not .M
2026-05-23 06:36:39 +00:00
760d120b1c
fix: typo + OperandMajorMode for TMEM budget probe
2026-05-23 06:35:55 +00:00
df3708e3e2
fix: LayoutEnum import from cutlass.utils
2026-05-23 06:35:03 +00:00
241aa0f334
fix import path for tcgen05
2026-05-23 06:34:30 +00:00
44f8b4c5ce
D1.2: TMEM budget probe script for hd=64,128,256,512
2026-05-23 06:33:26 +00:00
ddcb470005
debug: hd=64 with CUDA_LAUNCH_BLOCKING
2026-05-23 03:42:53 +00:00
730e4f4328
D1: test raw unnormalized output via epilogue_tma_store
2026-05-23 03:33:59 +00:00
d262764c84
test: paired atoms epilog from old commit 6ee28d8
2026-05-23 03:32:53 +00:00
9d8f4b8a05
D1: paired atoms epilogue (no TMEM round-trip)
...
Replace NO-OP round-trip + normalize + epilogue_tma_store with:
- get_tmem_load_op + get_smem_store_op paired atoms
- One-way TMEM→reg (normalize) →SMEM→GMEM
- Eliminates ~3% error from TMEM layout mismatch
- O rescale disabled (single KV tile only for now)
- Pre-computed TMA partitions outside if blocks
2026-05-23 03:29:51 +00:00
6b655f682c
d1: sweep hd=64,128,256
2026-05-23 03:26:10 +00:00
208dbe1d5c
fix: use mV.iterator
2026-05-23 03:25:29 +00:00
55b1217282
fix: use mQ not q for LayoutEnum
2026-05-23 03:24:58 +00:00
a81ff939ee
d1: add diagnostic script
2026-05-23 03:24:16 +00:00
ca51af99dd
D1: N-tile support for HEAD_DIM>256
...
- pv_n_tile = min(head_dim, 256) — MMA instruction N limit
- n_pv_tiles = head_dim // pv_n_tile — outer loop count
- V FMHA layout uses pv_n_tile (not head_dim) for N-tile slicing
- Test loops over N-tiles at Python level, kernel processes (128, pv_n_tile)
- For hd=512: 2 kernel launches with V[:,0:256] and V[:,256:512]
2026-05-23 03:22:23 +00:00
af51455db1
d1: add hd=512 test
2026-05-23 03:20:46 +00:00
