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e58980f80e
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fix: increase test timeout for TMEM kernel
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2026-05-28 06:41:59 +00:00 |
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99b35eb2de
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test: standalone CUDA test for FMHA SM100 (no PyTorch needed)
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2026-05-28 05:31:03 +00:00 |
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97df02ea07
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fix: -Xcompiler -fPIC for nvcc shared library
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2026-05-28 05:22:15 +00:00 |
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4dfb71bc20
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test: nvcc direct compilation test (avoid torch JIT __bf16 ICE)
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2026-05-28 05:21:41 +00:00 |
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09dfd4a41f
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fix: rename .cpp to .cu for CUDA compilation
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2026-05-28 05:16:41 +00:00 |
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4c194b7254
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fix: add CUDA include path for host compiler
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2026-05-28 05:15:48 +00:00 |
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f0660d0bd7
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fix: use C++20 for cuda_bf16.h compat
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2026-05-28 05:13:18 +00:00 |
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6bd3356582
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fix: include cuda_bf16.h unconditionally, add --expt-relaxed-constexpr
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2026-05-28 05:13:01 +00:00 |
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3eb432d064
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fix: CUTLASS path /root/cutlass
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2026-05-28 05:06:48 +00:00 |
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66d9f5c60f
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fix: --x cu for .cuh compilation
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2026-05-28 05:06:13 +00:00 |
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4dcd80ea0d
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fix: use full nvcc path
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2026-05-28 05:05:55 +00:00 |
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fac7275f2b
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test: nvcc compilation test for FMHA SM100 kernel
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2026-05-28 05:05:31 +00:00 |
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230c350c77
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FMHA SM100: Raw CUDA C++ decode kernel — initial skeleton
6-warp specialization using CUTLASS C++ atoms directly:
- tcgen05.mma for QK (SMEM→SMEM→TMEM) and PV (TMEM→SMEM→TMEM)
- TMEM accumulator with one-way correction epilogue (TMEM→regs→SMEM→GMEM)
- In-kernel O rescale via registers (fixes D1.5 TMEM round-trip!)
- D3/D4/D5c masks, NVFP4 quantize helpers, FP8 E4M3 encode
- PyTorch binding with head_dim template dispatch
This bypasses all CuTeDSL limitations: float→int, TMEM round-trip,
multi-CTA, hd=512 MLIR compilation hang.
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2026-05-28 05:04:44 +00:00 |
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