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360f76b970
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Performance audit fixes: eliminate CPU-GPU syncs
PERFORMANCE_AUDIT.md validation results:
1. Nvfp4Linear .item() sync (610/step) → FIXED: compute_amax_gsa_gpu kernel
2. MoE .item() sync (183/step) → FIXED: same kernel
3. SharedExpert .item() sync (122/step) → FIXED: same kernel
4. FMHA V clone → FIXED: V=K, transpose creates copy implicitly
5. torch.cuda.synchronize in moe_forward → FIXED: conditional on VERBOSE
6. RoPE 8x duplication → INVALIDATED: necessary for per-GPU HBM access
7. mHC BF16 bmm → INVALIDATED: 28K FLOPs, not a bottleneck
8. Router .float() cast → INVALIDATED: needed for FP32 topk, ~1μs
New files:
- dsv4/kernels/cuda/amax_gsa.cu: GPU-only amax→gsa kernel
- dsv4/ops/quantize.py: compute_amax_gsa_gpu() wrapper
Net effect: ~915 fewer CPU-GPU syncs per decode step
Remaining syncs: ~10 per layer (quantize kernel parameter) + diagnostics
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2026-06-01 20:40:19 +00:00 |
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3fb3c925af
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Restructure: cutedsl/ -> dsv4/ with proper layering
- Split bridge.py -> ops/quantize.py, ops/layouts.py, ops/gemm_runner.py
- Renamed classes: CuTeDSLNvfp4Linear -> Nvfp4Linear, etc.
- Moved kernel code to dsv4/kernels/ (gemm, attention, compressor, decode, cuda)
- Moved PyTorch bridges to dsv4/ops/
- Moved nn.Module layers to dsv4layers/
- Moved reference implementations to dsv4/reference/
- Moved vendored CUTLASS code to vendored/
- Archived ~190 debug tests to tests/archive/
- Kept ~15 canonical tests in tests/unit/
- Updated all import paths
- Added stubs for future components (model/, cache/, loader/)
- Updated pyproject.toml: dsv4-inference package name
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2026-05-21 17:30:44 +00:00 |
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