5290c91c35
fix quantize_nvfp4 kernel: use proven single-thread-per-CTA pattern from deinterleave_quantize.cu
...
The warp shuffle approach failed because __shfl_down_sync with 16 threads
has undefined behavior for the odd nibble. Use the same pattern as the
working deinterleave_quantize.cu: 1 CTA per 16-element block, 16 threads
per CTA, each thread reads all 16 elements sequentially and computes
amax + quantize + pack.
2026-05-25 16:21:44 +00:00
c2e3d15633
NVFP4-1.1 integration: GPU-only quantize kernel + MoE pipeline wiring
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- Add quantize_nvfp4.cu: BF16→FP4 GPU kernel (no CPU sync, warp shuffle amax)
- Add quantize_nvfp4_gpu() bridge in ops/quantize.py
- Fix deinterleave_quantize kernel path (dsv4/ops/kernels → dsv4/kernels/cuda)
- Wire GPU quantize into Nvfp4MoE._run_impl():
- L1 input: quantize_nvfp4_gpu (replaces quantize_activation_nvfp4)
- Fused SwiGLU L2: deinterleave_quantize_nvfp4_cuda (single kernel)
- Non-fused L2: quantize_nvfp4_gpu
- Add test_nvfp4_gpu_quantize.py for both kernels
2026-05-25 16:19:07 +00:00
6cc151097e
Revert D2 multi-CTA attempts - keeping per-head launch approach (works correctly)
2026-05-25 01:08:38 +00:00
34f5beb767
D2: fix gC coordinate to match 5-mode flat_divide result
2026-05-24 23:44:39 +00:00
a3559538cf
D2: try 6-mode coordinate for flat_divide result
2026-05-24 23:43:23 +00:00
6f371d6b31
D2: add flat_divide shape print, try different coordinate order
2026-05-24 23:42:04 +00:00
7007a9db79
D2: use flat_divide for runtime coordinate indexing (like CUTLASS)
2026-05-24 23:40:37 +00:00
3e340a0eee
D2: fix local_tile coordinate for 4D Q (2 rest modes, not 3)
2026-05-24 23:38:48 +00:00
b5cd1b88c9
D2: add shape debug print for mQ/mK
2026-05-24 23:37:10 +00:00
df3146eb53
D2: hardcode a_major=MN for multi-CTA (Q is always MN-major in FMHA)
2026-05-24 23:35:49 +00:00
e809e71253
D2: use tensor indexing q[0] instead of local_tile for layout extraction
2026-05-24 23:34:38 +00:00
49c4189195
D2: fix LayoutEnum for multi-dim Q (use head-0 view for layout)
2026-05-24 23:33:27 +00:00
2b76b691cb
fix: block_idx() returns tuple, use [1] for y
2026-05-24 23:29:59 +00:00
4c79e5533e
D2: add multi-CTA grid with block_idx_y for Q/O head indexing
2026-05-24 23:27:38 +00:00
e3e67c3992
NVFP4-3: enable 2-CTA UMMA when MMA tile M >= 256 (1.7-1.9x throughput)
2026-05-24 22:57:49 +00:00
e0339a92fc
D2: revert multi-CTA grid params (using per-head launch approach instead)
2026-05-24 22:52:21 +00:00
d563c93fc5
D2: add per-head launch test
2026-05-24 22:48:22 +00:00
0ca7b58a6a
D1: fully revert LSE change back to original sfw_idx==0 guard
2026-05-24 22:41:32 +00:00
4418e04a28
D1: revert per-row LSE to sfw_idx=0 for now (debugging D2 regression)
2026-05-24 22:28:11 +00:00
674c5b9c18
D1: fix per-row LSE output + add KV merge test v2 with per-row LSE
2026-05-24 22:21:51 +00:00
18f3274c0b
D1: DEBUG - NO-OP O rescale (multiply by 1.0) to test TMEM round-trip
2026-05-24 22:19:16 +00:00
0f30319e06
Revert "D1: move O rescale atoms outside const_expr guard (match CUTLASS pattern)"
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This reverts commit aaf21d8ac1
2026-05-24 22:15:38 +00:00
aaf21d8ac1
D1: move O rescale atoms outside const_expr guard (match CUTLASS pattern)
2026-05-24 22:07:18 +00:00
55c6903980
D1: fix O rescale identity tensor - use PV MMA shape not QK shape
2026-05-24 22:02:55 +00:00
a5fef69363
D1.4: Use cutlass.range(unroll=1) for k_sub loops in both TMA and MMA warps
2026-05-24 17:55:33 +00:00
25201d0c3d
D1.4: Guard LSE computation with const_expr(not normalize) - fixes BF16 type mismatch in regression test
2026-05-24 15:11:39 +00:00
7f64a11eea
D1.4: Switch k_sub from cutlass.range to Python range (unrolled at trace time)
2026-05-24 15:10:28 +00:00
6d7b8fed3e
D1.4: Fix tTMrO placeholder - define only inside const_expr block
2026-05-24 14:23:22 +00:00
7a4ff959bf
D1.4: Use cutlass.range loop for k_sub (reduce IR), guard O rescale with const_expr(n_kv_tiles>1)
2026-05-24 14:22:45 +00:00
592873b560
D1.4: Reduce pv_n_tile to 128 for hd=512 to fit SMEM budget (192KB)
2026-05-24 08:07:32 +00:00
e7c146dbfd
D1: Unrolled k_sub path (hardcoded k_sub=0,1) to avoid cutlass.range IR explosion
2026-05-24 07:03:14 +00:00
dd39c2ebdf
D1: Use cutlass.range for k_sub loops (CuTeDSL immutable handle)
2026-05-24 06:43:30 +00:00
2bf3ee40aa
D1: Fix kvh scoping - define before loops, consume V via pipeline
2026-05-24 06:42:26 +00:00
f2170fc1b3
D1: Fix kvb→kvh typo in PV GEMM
2026-05-24 06:41:25 +00:00
e2b914be5e
D1: Remove qh.commit() - pipeline handles commit internally
2026-05-24 06:40:10 +00:00
583c509bcd
D1: TMA producer uses acquire_and_advance + commit (no wait_and_advance)
2026-05-24 06:38:15 +00:00
3bf1e62b58
D1: Use same pipeline API as working code (acquire_and_advance) for k_sub path
2026-05-24 06:36:19 +00:00
85af7f4cf3
D1: Add PipelineState for k_sub TMA path
2026-05-24 05:02:17 +00:00
622089ad16
D1: Fix pipeline API for K sub-tile path (producer_acquire/commit)
2026-05-24 04:59:41 +00:00
b9e806f09d
D1: K sub-tile MMA path using pipeline barriers
2026-05-24 04:57:08 +00:00
98e974403c
D1: Fix TMA copies in k_sub path (no mbarrier, use cp_async wait)
2026-05-24 04:53:46 +00:00
e637d3ae73
D1: Add K sub-tile loop for hd=512 (const_expr guarded, hd≤256 path unchanged)
2026-05-24 04:51:51 +00:00
24b9310682
D1: Debug TMA partition shapes at hd=512
2026-05-24 04:43:12 +00:00
9201a844dd
D1: K sub-tiling - qk_mma_tiler K-dim = k_tile=256, SMEM fits at hd=512
2026-05-24 04:41:12 +00:00
d234297712
D1: Remove debug prints, clean up
2026-05-24 04:06:26 +00:00
3b63405ad4
D1: const_expr for sP layout selection (CuTeDSL)
2026-05-24 04:05:17 +00:00
1c8b043702
D1: Python if for sP layout (trace-time, not MLIR)
2026-05-24 04:04:27 +00:00
3aa8e5185a
D1: Tiny 4-mode sP placeholder for TMEM-P path
2026-05-24 04:03:28 +00:00
03ad730a9b
D1: Conditional sP allocation (saves 64KB SMEM for TMEM-P at hd=256)
2026-05-24 04:02:02 +00:00
975829e5c7
D1: Fix sP dummy allocation
2026-05-24 04:00:19 +00:00
