Commit Graph

242 Commits

Author SHA1 Message Date
6c73069cb9 D5b: Per-row LSE output + Python KV merge test
- Fix LSE output: all 128 rows now write (mLSE[sfw_idx, 0, 0])
  instead of only row 0 (mLSE[0])
- Each softmax thread (sfw_idx 0..127) independently writes its LSE
- This enables accurate Python-side KV merge for multi-KV-tile
- New test: test_d5b_perrow_lse.py with LSE verification + KV merge
2026-05-26 10:57:54 +00:00
e3e01071f4 fix: swa_len as Int32 scalar instead of CuTe tensor
CuTeDSL @cute.kernel cannot handle dynamic-shape tensors as parameters.
Pass swa_len as Int32 scalar instead of a 1D tensor.
This works for batch_size=1 (current config).
Updated D3 and D4 tests to pass swa_len as int.
2026-05-26 10:54:41 +00:00
df84420414 fix: add is_causal to FmhaKernel __init__ signature 2026-05-26 10:53:14 +00:00
841a3e87b2 D4: Causal mask on SWA branch
- Add is_causal flag to FmhaKernel constructor
- Mask positions where k_coord > m_coord to -inf (causal attention)
- Combined with D3 SWA mask: both conditions use OR logic
- Same tTMEM_LOADcS coordinate mapping as D3
- const_expr guarded: zero overhead when is_causal=False
- New test: test_d4_causal_mask.py with causal + combined masking
2026-05-26 10:52:30 +00:00
b6b581777a D3: In-kernel SWA sequence length masking
- Add apply_swa_mask flag to FmhaKernel constructor
- After TMEM load of S, use tTMEM_LOADcS coordinates to map register
  fragment positions to (row, col) in QK matrix
- Mask positions >= swa_lens[batch_idx] to -inf before softmax
- Supports multi-KV-tile (kt*128 + k_coord for absolute position)
- swa_lens parameter passed as CuTe tensor, indexed by block_idx_z
- Dummy tensor (max int) when swa_lens=None (no masking)
- New test: test_d3_inkernel_mask.py with proper in-kernel masking
- Replaces pre-masking approach (BF16 min on K) which can't produce -inf
2026-05-26 10:51:23 +00:00
d6a56342cc D3: add swa_lens parameter to FmhaKernel (in-kernel masking TBD) 2026-05-25 17:31:01 +00:00
f278348f44 D3: SWA mask with BF16 min pre-masking approach (K[invalid]=BF16_MIN → scores≈-inf) 2026-05-25 17:27:35 +00:00
dbe2ecbd41 D2: add num_query_heads/batch_size params + batch grid dimension
- Head-packed approach: Q is (n_h*T, hd, 1), kernel treats each row independently
- Grid: (1, 1, batch) — M dimension handled by head packing
- n_h=128, T=1 → M=128, one MMA tile, all heads in single CTA
- Tested: cos 0.999995 for both n_h=1 and n_h=128
2026-05-25 17:15:08 +00:00
13b5afc471 fully revert FmhaKernel changes to debug regression 2026-05-25 17:04:31 +00:00
0b9f9da2f7 revert grid change to debug regression 2026-05-25 17:03:19 +00:00
4826fa6afb D2: add num_query_heads/batch_size params + head-packed test
- FmhaKernel.__init__: add num_query_heads=1, batch_size=1
- Grid: (ceil_div(n_h*T, 128), 1, batch) for multi-CTA
- Test: head-packed multi-head (Q reshaped to (n_h*T, hd))
- n_h=1 regression, n_h=128 Pro decode, n_h=64 Flash, hd=128
2026-05-25 16:50:49 +00:00
5290c91c35 fix quantize_nvfp4 kernel: use proven single-thread-per-CTA pattern from deinterleave_quantize.cu
The warp shuffle approach failed because __shfl_down_sync with 16 threads
has undefined behavior for the odd nibble. Use the same pattern as the
working deinterleave_quantize.cu: 1 CTA per 16-element block, 16 threads
per CTA, each thread reads all 16 elements sequentially and computes
amax + quantize + pack.
2026-05-25 16:21:44 +00:00
c2e3d15633 NVFP4-1.1 integration: GPU-only quantize kernel + MoE pipeline wiring
- Add quantize_nvfp4.cu: BF16→FP4 GPU kernel (no CPU sync, warp shuffle amax)
- Add quantize_nvfp4_gpu() bridge in ops/quantize.py
- Fix deinterleave_quantize kernel path (dsv4/ops/kernels → dsv4/kernels/cuda)
- Wire GPU quantize into Nvfp4MoE._run_impl():
  - L1 input: quantize_nvfp4_gpu (replaces quantize_activation_nvfp4)
  - Fused SwiGLU L2: deinterleave_quantize_nvfp4_cuda (single kernel)
  - Non-fused L2: quantize_nvfp4_gpu
- Add test_nvfp4_gpu_quantize.py for both kernels
2026-05-25 16:19:07 +00:00
6cc151097e Revert D2 multi-CTA attempts - keeping per-head launch approach (works correctly) 2026-05-25 01:08:38 +00:00
34f5beb767 D2: fix gC coordinate to match 5-mode flat_divide result 2026-05-24 23:44:39 +00:00
a3559538cf D2: try 6-mode coordinate for flat_divide result 2026-05-24 23:43:23 +00:00
6f371d6b31 D2: add flat_divide shape print, try different coordinate order 2026-05-24 23:42:04 +00:00
7007a9db79 D2: use flat_divide for runtime coordinate indexing (like CUTLASS) 2026-05-24 23:40:37 +00:00
3e340a0eee D2: fix local_tile coordinate for 4D Q (2 rest modes, not 3) 2026-05-24 23:38:48 +00:00
b5cd1b88c9 D2: add shape debug print for mQ/mK 2026-05-24 23:37:10 +00:00
df3146eb53 D2: hardcode a_major=MN for multi-CTA (Q is always MN-major in FMHA) 2026-05-24 23:35:49 +00:00
e809e71253 D2: use tensor indexing q[0] instead of local_tile for layout extraction 2026-05-24 23:34:38 +00:00
49c4189195 D2: fix LayoutEnum for multi-dim Q (use head-0 view for layout) 2026-05-24 23:33:27 +00:00
2b76b691cb fix: block_idx() returns tuple, use [1] for y 2026-05-24 23:29:59 +00:00
4c79e5533e D2: add multi-CTA grid with block_idx_y for Q/O head indexing 2026-05-24 23:27:38 +00:00
e0339a92fc D2: revert multi-CTA grid params (using per-head launch approach instead) 2026-05-24 22:52:21 +00:00
d563c93fc5 D2: add per-head launch test 2026-05-24 22:48:22 +00:00
0ca7b58a6a D1: fully revert LSE change back to original sfw_idx==0 guard 2026-05-24 22:41:32 +00:00
4418e04a28 D1: revert per-row LSE to sfw_idx=0 for now (debugging D2 regression) 2026-05-24 22:28:11 +00:00
674c5b9c18 D1: fix per-row LSE output + add KV merge test v2 with per-row LSE 2026-05-24 22:21:51 +00:00
18f3274c0b D1: DEBUG - NO-OP O rescale (multiply by 1.0) to test TMEM round-trip 2026-05-24 22:19:16 +00:00
0f30319e06 Revert "D1: move O rescale atoms outside const_expr guard (match CUTLASS pattern)"
This reverts commit aaf21d8ac1.
2026-05-24 22:15:38 +00:00
aaf21d8ac1 D1: move O rescale atoms outside const_expr guard (match CUTLASS pattern) 2026-05-24 22:07:18 +00:00
55c6903980 D1: fix O rescale identity tensor - use PV MMA shape not QK shape 2026-05-24 22:02:55 +00:00
a5fef69363 D1.4: Use cutlass.range(unroll=1) for k_sub loops in both TMA and MMA warps 2026-05-24 17:55:33 +00:00
25201d0c3d D1.4: Guard LSE computation with const_expr(not normalize) - fixes BF16 type mismatch in regression test 2026-05-24 15:11:39 +00:00
7f64a11eea D1.4: Switch k_sub from cutlass.range to Python range (unrolled at trace time) 2026-05-24 15:10:28 +00:00
6d7b8fed3e D1.4: Fix tTMrO placeholder - define only inside const_expr block 2026-05-24 14:23:22 +00:00
7a4ff959bf D1.4: Use cutlass.range loop for k_sub (reduce IR), guard O rescale with const_expr(n_kv_tiles>1) 2026-05-24 14:22:45 +00:00
592873b560 D1.4: Reduce pv_n_tile to 128 for hd=512 to fit SMEM budget (192KB) 2026-05-24 08:07:32 +00:00
e7c146dbfd D1: Unrolled k_sub path (hardcoded k_sub=0,1) to avoid cutlass.range IR explosion 2026-05-24 07:03:14 +00:00
dd39c2ebdf D1: Use cutlass.range for k_sub loops (CuTeDSL immutable handle) 2026-05-24 06:43:30 +00:00
2bf3ee40aa D1: Fix kvh scoping - define before loops, consume V via pipeline 2026-05-24 06:42:26 +00:00
f2170fc1b3 D1: Fix kvb→kvh typo in PV GEMM 2026-05-24 06:41:25 +00:00
e2b914be5e D1: Remove qh.commit() - pipeline handles commit internally 2026-05-24 06:40:10 +00:00
583c509bcd D1: TMA producer uses acquire_and_advance + commit (no wait_and_advance) 2026-05-24 06:38:15 +00:00
3bf1e62b58 D1: Use same pipeline API as working code (acquire_and_advance) for k_sub path 2026-05-24 06:36:19 +00:00
85af7f4cf3 D1: Add PipelineState for k_sub TMA path 2026-05-24 05:02:17 +00:00
622089ad16 D1: Fix pipeline API for K sub-tile path (producer_acquire/commit) 2026-05-24 04:59:41 +00:00
b9e806f09d D1: K sub-tile MMA path using pipeline barriers 2026-05-24 04:57:08 +00:00