80b6b79f9e
NVFP4-1.1: FP4 quantization primitives for CuTeDSL kernels
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- fp8_e4m3_from_float32: manual FP8 E4M3 cast (bias=7, exp 0-15 valid,
NaN guard for exp=15/mant=7, mantissa overflow handling)
- fp8_e4m3_to_float32: dequantize FP8 E4M3 bit pattern back to Float32
- half_step_to_e2m1_idx: E2M1 step mapping (0-12 → 0-7)
- quantize_e2m1_nibble: per-element E2M1 quantize + sign + pack
- Verified 0/500 trial failures against Python reference
- Key fixes discovered during validation:
1. FP8 E4M3 bias is 7, NOT 8
2. Exponent range is 0-15 (exp=15/mant=7 is NaN; others valid)
3. Subnormal formula: val = m * 2^(-9) = m/512 (NOT m/1024)
4. Round-to-nearest-even (not round-half-up) for half_step and mantissa
5. Mantissa overflow (round to 8) must increment exponent
2026-05-28 03:39:55 +00:00
5012703bad
fix: add SwiGLU clamping to fused kernel (paper §4.2.3, CG-1)
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The fused SwiGLU kernel stored swiglu_limit but never applied it.
Paper §4.2.3: gate capped at swiglu_limit, linear clamped to [-limit, +limit].
Non-fused reference path already applies clamping correctly.
Fix: add fmin/fmax clamping in FP32 before BF16 conversion.
2026-05-23 06:32:54 +00:00
3fb3c925af
Restructure: cutedsl/ -> dsv4/ with proper layering
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- Split bridge.py -> ops/quantize.py, ops/layouts.py, ops/gemm_runner.py
- Renamed classes: CuTeDSLNvfp4Linear -> Nvfp4Linear, etc.
- Moved kernel code to dsv4/kernels/ (gemm, attention, compressor, decode, cuda)
- Moved PyTorch bridges to dsv4/ops/
- Moved nn.Module layers to dsv4layers/
- Moved reference implementations to dsv4/reference/
- Moved vendored CUTLASS code to vendored/
- Archived ~190 debug tests to tests/archive/
- Kept ~15 canonical tests in tests/unit/
- Updated all import paths
- Added stubs for future components (model/, cache/, loader/)
- Updated pyproject.toml: dsv4-inference package name
2026-05-21 17:30:44 +00:00
