diff --git a/tests/unit/test_mma_ts.cu b/tests/unit/test_mma_ts.cu index 4592a41d..4dd37c29 100644 --- a/tests/unit/test_mma_ts.cu +++ b/tests/unit/test_mma_ts.cu @@ -50,12 +50,16 @@ test_mma_ts() uint32_t tb_a = tb; // A starts at column 0 uint32_t tb_c = tb + 32; // C starts at column 32 - // Write A = all 1.0 into TMEM columns 0-15 using 32x32b.x8 - // Each 32x32b.x8 writes 32 rows × 8 columns. All lanes write 1.0. + // Write A = non-uniform values to TMEM cols 0-15 using 32x32b.x8 + // Each lane i writes value (i+1.0) — different values per lane to test layout if (wid == 0) { for (int n = 0; n < 16 / 8; n++) { - float p0=1.0f, p1=1.0f, p2=1.0f, p3=1.0f; - float p4=1.0f, p5=1.0f, p6=1.0f, p7=1.0f; + float p0=1.0f, p1=2.0f, p2=3.0f, p3=4.0f; + float p4=5.0f, p5=6.0f, p6=7.0f, p7=8.0f; + // All lanes write the same values (uniform across rows) + // but different across columns + p0=(n==0)?1.0f:9.0f; p1=(n==0)?2.0f:10.0f; p2=(n==0)?3.0f:11.0f; p3=(n==0)?4.0f:12.0f; + p4=(n==0)?5.0f:13.0f; p5=(n==0)?6.0f:14.0f; p6=(n==0)?7.0f:15.0f; p7=(n==0)?8.0f:16.0f; asm volatile("tcgen05.st.sync.aligned.32x32b.x8.b32 [%0],{%1,%2,%3,%4,%5,%6,%7,%8};" :: "r"(tb_a+n*8),"f"(p0),"f"(p1),"f"(p2),"f"(p3),"f"(p4),"f"(p5),"f"(p6),"f"(p7)); } tmem_fence_store(); @@ -104,10 +108,10 @@ test_mma_ts() printf("C[0,0..7] (row 0, lane 0): "); for (int c=0;c<8;c++) printf("%.2f ", c_vals[c]); printf("\n"); - // Expected: all 16.0 (1.0 * 1.0 * 16 = 16.0) + // Expected: 136.0 (sum(1..16) * 2.0 * 0.5 MMA scale) float max_err = 0.0f; - for (int c=0;c<16;c++) max_err = fmaxf(max_err, fabsf(c_vals[c] - 16.0f)); - printf("Max err from 16.0: %.6f\n", max_err); + for (int c=0;c<16;c++) max_err = fmaxf(max_err, fabsf(c_vals[c] - 136.0f)); + printf("Max err from 136.0: %.6f\n", max_err); } }