From efa0a156a027f97a77bab3950fe06af4b7a6c9d4 Mon Sep 17 00:00:00 2001
From: biondizzle <biondizzle@gmail.com>
Date: Wed, 20 May 2026 04:39:57 +0000
Subject: [PATCH] Update README with final kernel status

---
 README.md | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/README.md b/README.md
index 1e2a3355..a7826af2 100644
--- a/README.md
+++ b/README.md
@@ -134,11 +134,13 @@ CuTeDSL **does** support runtime conditionals on register tensors — the rule i
 
 | Step | What | Status |
 |------|------|--------|
-| 1 | Wire fused kernel into pipeline (skip BF16 GMEM round-trip) | 🔄 In progress |
-| 2 | NVFP4 quantize in epilogue (per-16-element amax, FP8 SF, FP4 pack) | 🔨 Next |
-| 3 | FP4 TMA store to padded L2 buffer | Not started |
-| 4 | FP8 SF TMA store through blockscaled layout | Not started |
-| 5 | End-to-end test with fused pipeline | Not started |
+| 1 | Wire fused kernel into pipeline | ✅ Done |
+| 2 | Custom CUDA de-interleave + quantize kernel (4.3x faster) | ✅ Done |
+| 3 | In-epilogue NVFP4 quantize (replace BF16 TMA with FP4 TMA) | 🔨 Future optimization |
+
+**Current pipeline:** Fused SwiGLU kernel → BF16 TMA store → Custom CUDA quantize → L2 GEMM
+**Cosine:** 0.988 (non-fused) / 0.988 (fused) vs BF16 reference
+**Quantize speedup:** 4.3x (0.043ms vs 0.184ms), saves ~8.5ms over 60 MoE layers
 
 ---