diff --git a/tests/fmha_v3_stage_c_example7.py b/tests/fmha_v3_stage_c_example7.py new file mode 100644 index 00000000..aa6ad2e1 --- /dev/null +++ b/tests/fmha_v3_stage_c_example7.py @@ -0,0 +1,545 @@ +""" +FMHA v3 Stage-C Multi-Tile (paired TMEM/SMEM atoms, reference-style epilogue). + +Two structural rules we had to learn the hard way: + +(A) Pipeline handle's `.count` is NOT a GMEM tile coordinate. Whatever it is at + runtime (phase, wrapped slot index, internal state), it is not a global + tile counter and TMA copies don't consume it as one. Use the loop + induction variable for GMEM, handle.index for SMEM. + +(B) Hand-constructed TMEM load/store atoms (Ld32x32bOp + St32x32bOp built + independently) DO NOT preserve register tile shape across a round-trip. + A no-op TMEM-load-then-TMEM-store visibly corrupts data. Use the paired + atoms from `utils.sm100.get_tmem_load_op` + `get_smem_store_op` — they + are configured together for the same (mma_tiler, layout, dtype) combo + and the register tile shape lines up. This is what the CUTLASS Blackwell + FMHA reference does in `correction_epilog`. + +Kernel structure: + +1. Combined K+V pipeline (tx_count = K_bytes + V_bytes; one acquire per kt; + K and V share the same barrier slot). SMEM slot via kvh.index, GMEM via + the cutlass.range loop variable. + +2. Reference-style epilogue (TMEM → reg → scale by 1/row_sum → FP32→BF16 in + reg → SMEM via paired atoms → TMA SMEM→GMEM). One pass, no TMEM + round-trip, no `epilogue_tma_store` helper. Inline TMA store + named + barrier sync to substitute for what the helper would have done. + +3. Online softmax row_max / row_sum tracking is correct, but the per-tile + in-place TMEM O rescale (multiplying existing O by exp2(old_max - new_max) + before PV[kt]) is currently DISABLED. Fixing that requires applying the + same paired-atom pattern to a separate scratch SMEM buffer and bouncing + PV's accumulator through it, which is substantial work. For now, the + kernel is correct when row_max growth across tiles is mild. Long n with + pronounced max growth will drift; the fix path is well-defined. + +4. final_o_bar (32 MMA + 128 softmax threads). MMA arrives between + acc_pipe.producer_commit and producer_tail; softmax arrives_and_waits + before reading O. Order: producer_commit → final_o_bar.arrive() → + producer_tail (reverse deadlocks). +""" +import torch, cutlass, cutlass.cute as cute, cutlass.utils as utils, cutlass.pipeline as pipeline +from cutlass.cute.nvgpu import cpasync, tcgen05 +from cutlass import Float32, BFloat16, Int32, Boolean, const_expr +from cutlass.utils import LayoutEnum +from cutlass.utils.tmem_allocator import find_tmem_tensor_col_offset +import cuda.bindings.driver as cuda +import cutlass.torch as ct +import math + +HEAD_DIM = 64 + + +class FmhaV3StageCMulti: + def __init__(self, s_k=128, scale_softmax=None): + # s_k MUST equal actual sequence length n. + self.s_k = s_k + self.acc_dtype = Float32; self.qk_acc_dtype = Float32 + self.q_dtype = BFloat16; self.o_dtype = BFloat16; self.c_dtype = BFloat16 + self.use_2cta_instrs = False; self.epilog_sync_bar_id = 1 + self.cluster_shape_mn = (1, 1); self.cta_group = tcgen05.CtaGroup.ONE + self.epilogue_warp_id = (0,1,2,3); self.mma_warp_id = 4; self.tma_warp_id = 5 + self.threads_per_cta = 192; self.num_c_stage = 2 + self.kv_stage = 2; self.q_stage = 1; self.num_c_stage = 2 + self.scale_softmax = scale_softmax if scale_softmax is not None else 1.0 / math.sqrt(HEAD_DIM) + self.scale_softmax_log2 = self.scale_softmax * math.log2(math.e) + + def _setup(self, qk_mma, pv_mma): + qk_ik = cute.size(qk_mma.shape_mnk, mode=[2]) + self.qk_mma_tiler = (128, 128, qk_ik * 4) + pv_ik = cute.size(pv_mma.shape_mnk, mode=[2]) + self.pv_mma_tiler = (128, HEAD_DIM, pv_ik * (128 // pv_ik)) + self.mma_tiler = self.qk_mma_tiler + self.cluster_layout_vmnk = cute.tiled_divide(cute.make_layout((1,1,1)), (qk_mma.thr_id.shape,)) + self.cta_tile_shape_mnk = (self.qk_mma_tiler[0]//cute.size(qk_mma.thr_id.shape), HEAD_DIM, self.qk_mma_tiler[2]) + self.c_layout = LayoutEnum.ROW_MAJOR + self.epi_tile = utils.sm100.compute_epilogue_tile_shape(self.cta_tile_shape_mnk, False, self.c_layout, self.o_dtype) + self.num_ab_stage = 1; self.num_acc_stage = 1 + self.q_smem_s = utils.sm100.make_smem_layout_a(qk_mma, self.qk_mma_tiler, self.q_dtype, self.q_stage) + self.k_smem_s = utils.sm100.make_smem_layout_b(qk_mma, self.qk_mma_tiler, self.q_dtype, self.kv_stage) + self.v_smem_s = utils.sm100.make_smem_layout_b(pv_mma, self.pv_mma_tiler, self.q_dtype, self.kv_stage) + self.c_smem_s = utils.sm100.make_smem_layout_epi(self.o_dtype, self.c_layout, self.epi_tile, 2) + self.p_tmem_s = utils.sm100.make_smem_layout_a(pv_mma, self.pv_mma_tiler, self.q_dtype, 1) + qk_thr = qk_mma.get_slice(0); qk_as = qk_thr.partition_shape_C(self.qk_mma_tiler[:2]) + tStS = qk_thr.make_fragment_C(qk_as) + pv_thr = pv_mma.get_slice(0); pv_as = pv_thr.partition_shape_C(self.pv_mma_tiler[:2]) + tOtO = pv_thr.make_fragment_C(pv_as) + self.tmem_s0_offset = 0; self.tmem_p0_offset = 32 + p_cols_fp32 = self.pv_mma_tiler[2] * self.q_dtype.width // self.qk_acc_dtype.width + p_end = self.tmem_p0_offset + p_cols_fp32 + s_cols = self.qk_mma_tiler[1] + o_after = max(s_cols, p_end) + self.tmem_o0_offset = ((o_after + 31) // 32) * 32 + o_cols = find_tmem_tensor_col_offset(tOtO) + total = self.tmem_o0_offset + o_cols + self.num_tmem_alloc_cols = 1 + while self.num_tmem_alloc_cols < total: + self.num_tmem_alloc_cols *= 2 + cta = cute.size(qk_mma.thr_id.shape) + q_s = cute.slice_(self.q_smem_s,(None,None,None,0)) + k_s = cute.slice_(self.k_smem_s,(None,None,None,0)) + v_s = cute.slice_(self.v_smem_s,(None,None,None,0)) + self.q_tx_bytes = cute.size_in_bytes(self.q_dtype, q_s) * cta + # Combined barrier: tx_count covers BOTH K and V transfers per acquire. + self.kv_tx_bytes = (cute.size_in_bytes(self.q_dtype, k_s) + + cute.size_in_bytes(self.q_dtype, v_s)) * cta + + @cute.jit + def __call__(self, q, k, v, c, stream): + self.q_dtype = q.element_type; self.o_dtype = c.element_type; self.c_dtype = self.o_dtype + self.a_major = LayoutEnum.from_tensor(q).mma_major_mode() + self.b_major = LayoutEnum.from_tensor(k).mma_major_mode() + v_fmha = cute.make_tensor( + v.iterator, + cute.make_layout( + (HEAD_DIM, self.s_k, 1), + stride=(1, HEAD_DIM, HEAD_DIM * self.s_k), + ), + ) + self.v_major = LayoutEnum.from_tensor(v_fmha).mma_major_mode() + self.c_layout = LayoutEnum.from_tensor(c) + qk_mma = utils.sm100.make_trivial_tiled_mma(self.q_dtype, self.q_dtype, self.a_major, self.b_major, self.qk_acc_dtype, self.cta_group, (128,128), tcgen05.OperandSource.SMEM) + pv_mma = utils.sm100.make_trivial_tiled_mma(self.q_dtype, self.q_dtype, cute.nvgpu.OperandMajorMode.K, self.v_major, self.qk_acc_dtype, self.cta_group, (128,HEAD_DIM), tcgen05.OperandSource.TMEM) + self._setup(qk_mma, pv_mma) + q_s = cute.slice_(self.q_smem_s,(None,None,None,0)); k_s = cute.slice_(self.k_smem_s,(None,None,None,0)); v_s = cute.slice_(self.v_smem_s,(None,None,None,0)) + tma_q,mQ = cute.nvgpu.make_tiled_tma_atom_A(utils.sm100.cluster_shape_to_tma_atom_A(self.cluster_shape_mn,qk_mma.thr_id),q,q_s,self.qk_mma_tiler,qk_mma,self.cluster_layout_vmnk.shape) + tma_k,mK = cute.nvgpu.make_tiled_tma_atom_B(utils.sm100.cluster_shape_to_tma_atom_B(self.cluster_shape_mn,qk_mma.thr_id),k,k_s,self.qk_mma_tiler,qk_mma,self.cluster_layout_vmnk.shape) + tma_v,mV = cute.nvgpu.make_tiled_tma_atom_B(utils.sm100.cluster_shape_to_tma_atom_B(self.cluster_shape_mn,pv_mma.thr_id),v_fmha,v_s,self.pv_mma_tiler,pv_mma,self.cluster_layout_vmnk.shape) + epi_s = cute.select(self.c_smem_s,mode=[0,1]) + tma_c,mC = cpasync.make_tiled_tma_atom(cpasync.CopyBulkTensorTileS2GOp(),c,epi_s,self.epi_tile) + self._kernel(qk_mma,pv_mma,tma_q,mQ,tma_k,mK,tma_v,mV,tma_c,mC,self.cluster_layout_vmnk,self.q_smem_s,self.k_smem_s,self.v_smem_s,self.p_tmem_s,self.c_smem_s,self.epi_tile).launch(grid=(1,1,1),block=[self.threads_per_cta,1,1],stream=stream) + + @cute.kernel + def _kernel(self, qk_mma, pv_mma, tma_q, mQ, tma_k, mK, tma_v, mV, tma_c, mC, cl_vmnk, q_smem_s, k_smem_s, v_smem_s, p_tmem_s, c_smem_s, epi_tile): + warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx()) + tidx,_,_ = cute.arch.thread_idx() + if warp_idx == self.tma_warp_id: + cpasync.prefetch_descriptor(tma_q); cpasync.prefetch_descriptor(tma_k); cpasync.prefetch_descriptor(tma_v); cpasync.prefetch_descriptor(tma_c) + + @cute.struct + class SS: + q_bar: cute.struct.MemRange[cutlass.Int64, self.q_stage*2] + kv_bar: cute.struct.MemRange[cutlass.Int64, self.kv_stage*2] + s_bar: cute.struct.MemRange[cutlass.Int64, 2] + acc_bar: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage*2] + tmem_dealloc: cutlass.Int64; holding: cutlass.Int32 + smem = utils.SmemAllocator(); st = smem.allocate(SS) + + qp,qc = pipeline.PipelineTmaUmma.create(barrier_storage=st.q_bar.data_ptr(),num_stages=self.q_stage,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,1),tx_count=self.q_tx_bytes,cta_layout_vmnk=cl_vmnk,defer_sync=True).make_participants() + # Combined K+V pipeline: each stage carries BOTH K and V loaded together. + kvp,kvc = pipeline.PipelineTmaUmma.create(barrier_storage=st.kv_bar.data_ptr(),num_stages=self.kv_stage,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,1),tx_count=self.kv_tx_bytes,cta_layout_vmnk=cl_vmnk,defer_sync=True).make_participants() + s_prod,s_cons = pipeline.PipelineUmmaAsync.create(barrier_storage=st.s_bar.data_ptr(),num_stages=1,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,32*len(self.epilogue_warp_id))).make_participants() + softmax_done_bar = pipeline.NamedBarrier(barrier_id=3, num_threads=32 + 32*len(self.epilogue_warp_id)) + # Final-O sync: MMA arrives between producer_commit and producer_tail; + # softmax arrives_and_waits before reading O for the final normalize. + final_o_bar = pipeline.NamedBarrier(barrier_id=4, num_threads=32 + 32*len(self.epilogue_warp_id)) + acc_pipe = pipeline.PipelineUmmaAsync.create(barrier_storage=st.acc_bar.data_ptr(),num_stages=self.num_acc_stage,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,len(self.epilogue_warp_id)),cta_layout_vmnk=cl_vmnk,defer_sync=True) + tmem_bar = pipeline.NamedBarrier(barrier_id=2,num_threads=32*len((self.mma_warp_id,*self.epilogue_warp_id))) + tmem = utils.TmemAllocator(st.holding.ptr,barrier_for_retrieve=tmem_bar,allocator_warp_id=self.epilogue_warp_id[0],is_two_cta=cute.size(qk_mma.thr_id.shape)==2,two_cta_tmem_dealloc_mbar_ptr=st.tmem_dealloc.ptr) + pipeline.pipeline_init_arrive(cluster_shape_mn=cl_vmnk,is_relaxed=True) + + sQ = smem.allocate_tensor(element_type=self.q_dtype,layout=q_smem_s.outer,byte_alignment=128,swizzle=q_smem_s.inner) + sK = smem.allocate_tensor(element_type=self.q_dtype,layout=k_smem_s.outer,byte_alignment=128,swizzle=k_smem_s.inner) + sV = smem.allocate_tensor(element_type=self.q_dtype,layout=v_smem_s.outer,byte_alignment=128,swizzle=v_smem_s.inner) + sC = smem.allocate_tensor(element_type=self.o_dtype,layout=c_smem_s.outer,byte_alignment=128,swizzle=c_smem_s.inner) + + gQ = cute.local_tile(mQ,cute.slice_(self.qk_mma_tiler,(None,0,None)),(None,None,None)) + gK = cute.local_tile(mK,cute.slice_(self.qk_mma_tiler,(0,None,None)),(None,None,None)) + gV = cute.local_tile(mV,cute.slice_(self.pv_mma_tiler,(0,None,None)),(None,None,None)) + gC = cute.local_tile(mC,cute.slice_(self.pv_mma_tiler,(None,None,0)),(None,None,None)) + n_kv_tiles = cute.size(gK, mode=[3]) + + qk_thr = qk_mma.get_slice(0); pv_thr = pv_mma.get_slice(0) + tCgQ = qk_thr.partition_A(gQ); tCgK = qk_thr.partition_B(gK) + tCgV = pv_thr.partition_B(gV); tCgC = pv_thr.partition_C(gC) + a_lay = cute.make_layout(cute.slice_(cl_vmnk,(0,0,None,0)).shape) + tAsQ,tAgQ = cpasync.tma_partition(tma_q,0,a_lay,cute.group_modes(sQ,0,3),cute.group_modes(tCgQ,0,3)) + b_lay = cute.make_layout(cute.slice_(cl_vmnk,(0,None,0,0)).shape) + tBsK,tBgK = cpasync.tma_partition(tma_k,0,b_lay,cute.group_modes(sK,0,3),cute.group_modes(tCgK,0,3)) + tVsV,tVgV = cpasync.tma_partition(tma_v,0,b_lay,cute.group_modes(sV,0,3),cute.group_modes(tCgV,0,3)) + tAgQ = tAgQ[(None,0,None,0)]; tBgK = tBgK[(None,None,0,0)]; tVgV = tVgV[(None,0,None,0)] + + tCrQ = qk_mma.make_fragment_A(sQ); tCrK = qk_mma.make_fragment_B(sK) + tCrV = pv_mma.make_fragment_B(sV) + + qk_as = qk_thr.partition_shape_C(self.qk_mma_tiler[:2]) + tStS = qk_thr.make_fragment_C(qk_as) + tStS0 = cute.make_tensor(tStS.iterator + self.tmem_s0_offset, tStS.layout) + pv_as = pv_thr.partition_shape_C(self.pv_mma_tiler[:2]) + tOtO = pv_thr.make_fragment_C(pv_as) + tOtO0 = cute.make_tensor(tOtO.iterator + self.tmem_o0_offset, tOtO.layout) + + tP = cute.make_tensor(tStS.iterator, p_tmem_s.outer) + tOrP_base = pv_thr.make_fragment_A(tP) + tOrP = tOrP_base[(None,None,None,0)] + tOrP0 = cute.make_tensor( + tOrP.iterator + self.qk_acc_dtype.width // self.q_dtype.width * self.tmem_p0_offset, + tOrP.layout) + + tCtS_fake = qk_mma.make_fragment_C(cute.append(qk_as, self.num_acc_stage)) + tCtO_fake = pv_mma.make_fragment_C(cute.append(pv_as, self.num_acc_stage)) + pipeline.pipeline_init_wait(cluster_shape_mn=cl_vmnk) + + # ===== TMA LOAD warp ===== + # GMEM tile coordinate: use the cutlass.range induction variable kt + # directly. CuTeDSL's `cutlass.range` doesn't auto-detect a Python `+=` + # rebinding as a loop-carried iter_args update — the JIT traces the + # body once and captures whatever value `kv_coord` had at trace time, + # so an outer `kv_coord = Int32(0)` plus a `kv_coord += 1` inside the + # loop bakes 0 into every iteration's TMA descriptor at runtime. + # The induction variable IS the loop-carried state, properly tracked. + if warp_idx == self.tma_warp_id: + qp.reset(); qh = qp.acquire_and_advance() + cute.copy(tma_q, tAgQ[(None, Int32(0))], tAsQ[(None, qh.index)], tma_bar_ptr=qh.barrier) + qp.tail() + kvp.reset(); pk = kvp.try_acquire() + for kt in cutlass.range(0, n_kv_tiles, 1, unroll=1): + kvh = kvp.acquire_and_advance(pk) + cute.copy(tma_k, tBgK[(None, kt)], tBsK[(None, kvh.index)], tma_bar_ptr=kvh.barrier) + cute.copy(tma_v, tVgV[(None, kt)], tVsV[(None, kvh.index)], tma_bar_ptr=kvh.barrier) + pk = cutlass.Boolean(1) + kvp.tail() + + # ===== MMA warp ===== + # One wait per kt; same slot index used for both K (QK) and V (PV). + # Release happens AFTER PV — combined slot stays held across QK+PV. + if warp_idx == self.mma_warp_id: + tmem.wait_for_alloc() + qc.reset(); qh = qc.wait_and_advance(); qh.release() + kvc.reset(); pk = kvc.try_wait() + acc_st = pipeline.make_pipeline_state(pipeline.PipelineUserType.Producer, self.num_acc_stage) + acc_pipe.producer_acquire(acc_st) + for kt in range(n_kv_tiles): + kvh = kvc.wait_and_advance(pk); pk = cutlass.Boolean(1) + sh = s_prod.acquire_and_advance() + qk_mma.set(tcgen05.Field.ACCUMULATE, False) + for kb in cutlass.range(cute.size(tCrQ, mode=[2]), unroll_full=True): + cute.gemm(qk_mma, tStS0, tCrQ[(None,None,kb,0)], tCrK[(None,None,kb,kvh.index)], tStS0) + qk_mma.set(tcgen05.Field.ACCUMULATE, True) + cute.arch.fence_view_async_tmem_store() + sh.commit() + softmax_done_bar.arrive_and_wait() + pv_mma.set(tcgen05.Field.ACCUMULATE, kt != 0) + for kb in cutlass.range(cute.size(tOrP0, mode=[2]), unroll_full=True): + cute.gemm(pv_mma, tOtO0, tOrP0[(None,None,kb)], tCrV[(None,None,kb,kvh.index)], tOtO0) + pv_mma.set(tcgen05.Field.ACCUMULATE, True) + cute.arch.fence_view_async_tmem_store() + kvh.release() + acc_pipe.producer_commit(acc_st); acc_st.advance() + # Signal softmax FIRST so it can run normalize + epilogue. Then + # wait for the epilogue's consumer-release in producer_tail. + # Reverse order deadlocks: producer_tail blocks waiting for + # consumer release; softmax blocks at final_o_bar waiting for + # MMA arrive; the epilogue (which does the release) is gated + # behind softmax's final_o_bar wait. Cycle. + final_o_bar.arrive() + acc_pipe.producer_tail(acc_st) + + # ===== SOFTMAX + EPILOGUE warps ===== + if warp_idx < self.mma_warp_id: + tmem.allocate(self.num_tmem_alloc_cols) + tmem.wait_for_alloc() + tmem_ptr = tmem.retrieve_ptr(self.qk_acc_dtype) + sfw_idx = tidx % (32 * len(self.epilogue_warp_id)) + + # S load + tmem_load_atom = cute.make_copy_atom(tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)), self.qk_acc_dtype) + tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tStS0) + thr_load = tiled_tmem_load.get_slice(sfw_idx) + tTMEM_LOADtS = thr_load.partition_S(tStS0) + cS = cute.make_identity_tensor((self.qk_mma_tiler[0], self.qk_mma_tiler[1])) + tScS = qk_thr.partition_C(cS) + tTMEM_LOADcS = thr_load.partition_D(tScS) + + # P store + p_cols_fp32 = self.pv_mma_tiler[2] * self.q_dtype.width // self.qk_acc_dtype.width + tStP_layout = cute.composition(tStS.layout, cute.make_layout((self.pv_mma_tiler[0], p_cols_fp32))) + tStP0 = cute.make_tensor(tStS.iterator + self.tmem_p0_offset, tStP_layout) + tmem_store_atom = cute.make_copy_atom(tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(32)), self.qk_acc_dtype) + tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tStP0) + thr_store = tiled_tmem_store.get_slice(sfw_idx) + tTMEM_STOREtP = thr_store.partition_D(tStP0) + tScP_layout = cute.composition(tScS.layout, cute.make_layout((self.pv_mma_tiler[0], p_cols_fp32))) + tScP = cute.make_tensor(tScS.iterator, tScP_layout) + tTMEM_STOREcP = thr_store.partition_S(tScP) + + row_max = -Float32.inf + row_sum = Float32(0.0) + scale_log2 = Float32(self.scale_softmax_log2) + + # Per-tile softmax loop. + # Online softmax row_max/row_sum tracking is maintained, but the + # in-place TMEM O rescale (which would multiply existing O by + # exp2(old_max - new_max) before PV[kt]) is DISABLED — this is the + # correctness compromise for hand-paired TMEM atoms not working. + # The fix path is to integrate the rescale into the same paired + # tmem_load/smem_store epilogue pattern we use below for normalize. + # For now: kernel is correct when row_max growth across tiles is + # mild (typical for short n with random data); for very long n + # the missing rescale shows as accuracy drift. + for kt in range(n_kv_tiles): + si_handle = s_cons.wait_and_advance() + + # Load S[kt] + tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcS.shape, self.qk_acc_dtype) + cute.copy(tiled_tmem_load, tTMEM_LOADtS, tTMEM_LOADrS) + cute.arch.fence_view_async_tmem_load() + + # Pass 1: update row_max (in log2-domain, fused with scale). + old_row_max = row_max + frg_cnt = 4 + frg_tile = cute.size(tTMEM_LOADrS) // frg_cnt + tTMEM_LOADrS_frg = cute.logical_divide(tTMEM_LOADrS, cute.make_layout(frg_tile)) + for j in range(frg_cnt): + for k in range(cute.size(tTMEM_LOADrS_frg, mode=[0])): + row_max = cute.arch.fmax(row_max, tTMEM_LOADrS_frg[k, j] * scale_log2) + + row_max_safe = row_max + if row_max == -cutlass.Float32.inf: + row_max_safe = Float32(0.0) + + # row_sum rescale (correct even without O rescale — row_sum + # is a register variable, not in TMEM). + # row_max is already in scaled domain, so no extra scale_log2. + acc_scale_ = old_row_max - row_max_safe + acc_scale = cute.math.exp2(acc_scale_, fastmath=True) + if old_row_max == -cutlass.Float32.inf: + acc_scale = Float32(0.0) + row_sum *= acc_scale + + # Pass 2: P = exp2((S - new_max) * log2), accumulate row_sum, + # store BF16 P through the FP32-backed register bridge. + rP_words = cute.make_rmem_tensor(tTMEM_STOREcP.shape, self.qk_acc_dtype) + rP_bf16 = cute.make_tensor(cute.recast_ptr(rP_words.iterator, dtype=self.q_dtype), tTMEM_LOADrS.layout) + minus_row_max = Float32(0.0) - row_max_safe + + rP_bf16_frg = cute.logical_divide(rP_bf16, cute.make_layout(frg_tile)) + for j in range(frg_cnt): + for k in range(cute.size(tTMEM_LOADrS_frg, mode=[0])): + tTMEM_LOADrS_frg[k, j] = tTMEM_LOADrS_frg[k, j] * scale_log2 + minus_row_max + tTMEM_LOADrS_frg[k, j] = cute.math.exp2(tTMEM_LOADrS_frg[k, j], fastmath=True) + row_sum = row_sum + tTMEM_LOADrS_frg[k, j] + s_vec = tTMEM_LOADrS_frg[None, j].load() + rP_bf16_frg[None, j].store(s_vec.to(self.q_dtype)) + + cute.copy(tiled_tmem_store, rP_words, tTMEM_STOREtP) + cute.arch.fence_view_async_tmem_store() + + si_handle.release() + softmax_done_bar.arrive() + + # === Reference-style scaled epilogue (no TMEM round-trip) === + # + # Pattern (mirrors CUTLASS Blackwell FMHA reference's + # correction_epilog): for each column sub-tile, + # 1. TMEM -> registers via PAIRED tmem_load atom + # 2. scale in registers (1/row_sum) + # 3. FP32 -> BF16 conversion in registers + # 4. registers -> SMEM via PAIRED smem_store atom + # Then TMA SMEM -> GMEM as a separate step. + # + # Critical: the load and store atoms MUST be a matched pair. + # Independently constructed Ld32x32bOp + St32x32bOp atoms (the + # previous code) don't preserve the register tile shape, so even a + # no-op load+store corrupts data. Using utils.blackwell_helpers + # (sm100_utils) gives a paired set keyed to the same epi_subtile. + + # Wait for MMA's PV[N-1] to commit before reading O. + final_o_bar.arrive_and_wait() + + # Build paired TMEM load + SMEM store atoms via sm100_utils + # (the same path the reference uses). These two atoms share the + # same register-tile shape, so reg data round-trips losslessly. + # + # epi_subtile narrows the C-tile to a column slab matching one + # SMEM stage; smaller subtiles = more iterations but lower + # register pressure. Use the kernel's pre-computed self.epi_tile + # (computed from compute_epilogue_tile_shape in _setup). + epi_subtile = self.epi_tile + + # The TMEM tensor we load from is the full O accumulator at the + # PV offset; partition it column-wise into epi_subtile chunks. + tOtO_epi = cute.logical_divide( + tOtO0, + cute.make_layout((self.pv_mma_tiler[0], epi_subtile[1])), + ) + # Corresponding identity coord tensor (for partitioning). + cO_full = cute.make_identity_tensor( + (self.pv_mma_tiler[0], self.pv_mma_tiler[1]) + ) + tOcO_full = pv_thr.partition_C(cO_full) + tOcO_epi = cute.logical_divide( + tOcO_full, + cute.make_layout((self.pv_mma_tiler[0], epi_subtile[1])), + ) + # And the SMEM destination tensor (stage 0 of sC). + tOsO = pv_thr.partition_C(sC[None, None, 0]) + tOsO_epi = cute.logical_divide( + tOsO, + cute.make_layout((self.pv_mma_tiler[0], epi_subtile[1])), + ) + + # Paired atoms via sm100_utils. get_tmem_load_op returns an atom + # configured for the (mma_tiler, dtype, epi_subtile) combo; the + # matching smem_store atom is derived from the resulting tiled + # tmem load so that the register tile shape lines up. + tmem_load_op = utils.sm100.get_tmem_load_op( + self.pv_mma_tiler, + self.c_layout, + self.o_dtype, + self.acc_dtype, + epi_subtile, + use_2cta_instrs=False, + ) + tiled_tmem_load_o = tcgen05.make_tmem_copy( + tmem_load_op, tOtO_epi[(None, None), 0] + ) + thr_tmem_load_o = tiled_tmem_load_o.get_slice(sfw_idx) + smem_store_op = utils.sm100.get_smem_store_op( + self.c_layout, self.o_dtype, self.acc_dtype, tiled_tmem_load_o + ) + tiled_smem_store_o = cute.make_tiled_copy_D( + smem_store_op, tiled_tmem_load_o + ) + + tTMEM_LOADtO = thr_tmem_load_o.partition_S(tOtO_epi[(None, None), None]) + tTMEM_LOADsO = thr_tmem_load_o.partition_D(tOsO_epi[(None, None), None]) + tTMEM_LOADcO = thr_tmem_load_o.partition_D(tOcO_epi[(None, None), None]) + + # Scale = 1/row_sum (fused into the TMEM->SMEM pass). + inv_row_sum = Float32(1.0) / row_sum + + n_epi_tiles = self.pv_mma_tiler[1] // epi_subtile[1] + for i in range(n_epi_tiles): + # Load this column sub-tile from TMEM into registers. + tTMrO = cute.make_rmem_tensor( + tTMEM_LOADcO[None, 0, 0, i].shape, self.acc_dtype + ) + cute.copy(tiled_tmem_load_o, tTMEM_LOADtO[None, 0, 0, i], tTMrO) + + # Apply normalization in FP32 registers, before dtype conv. + for k in cutlass.range(cute.size(tTMrO), vectorize=True): + tTMrO[k] = tTMrO[k] * inv_row_sum + + # Convert FP32 -> output dtype (BF16) in registers. + tSMrO = cute.make_rmem_tensor(tTMrO.shape, self.o_dtype) + o_vec = tTMrO.load() + tSMrO.store(o_vec.to(self.o_dtype)) + + # Store registers -> SMEM via paired atom. + cute.copy( + tiled_smem_store_o, tSMrO, tTMEM_LOADsO[None, 0, 0, i] + ) + + cute.arch.fence_view_async_tmem_load() + # Async-proxy fence so the TMA store sees the SMEM writes. + cute.arch.fence_proxy("async.shared", space="cta") + cute.arch.barrier_arrive( + barrier_id=self.epilog_sync_bar_id, + number_of_threads=32 * len(self.epilogue_warp_id), + ) + cute.arch.barrier_wait( + barrier_id=self.epilog_sync_bar_id, + number_of_threads=32 * len(self.epilogue_warp_id), + ) + + # TMA SMEM -> GMEM. One warp issues the copy; the rest waited at + # the named barrier above. (Match epilogue_tma_store's behavior + # with all-thread arrive.) + if warp_idx == self.epilogue_warp_id[0]: + # Partition sC and gC for TMA. + tOsO_tma, tOgO_tma = cpasync.tma_partition( + tma_c, + 0, + cute.make_layout(1), + cute.group_modes(sC, 0, 2), + cute.group_modes(tCgC, 0, 2), + ) + # tOgO_tma still has the trailing tile/batch coords; we want + # the first (and only) tile here. + cute.copy(tma_c, tOsO_tma[None, 0], tOgO_tma[None, 0, 0, 0]) + cute.arch.cp_async_bulk_commit_group() + cute.arch.cp_async_bulk_wait_group(0, read=True) + + # Release the acc pipe so MMA's producer_tail can complete. + acc_cons_st = pipeline.make_pipeline_state( + pipeline.PipelineUserType.Consumer, self.num_acc_stage + ) + acc_pipe.consumer_release(acc_cons_st) + + tmem.relinquish_alloc_permit() + tmem.free(tmem_ptr) + + +def test(): + torch.manual_seed(42) + for n in [128, 256, 512, 1024]: + torch.manual_seed(42) + m, hd = 128, HEAD_DIM + q = torch.randn(m, hd, 1, dtype=torch.bfloat16, device='cuda') + k = torch.randn(n, hd, 1, dtype=torch.bfloat16, device='cuda') + v = torch.randn(n, hd, dtype=torch.bfloat16, device='cuda') + v_kernel = v.unsqueeze(-1) + c = torch.zeros(m, hd, 1, dtype=torch.bfloat16, device='cuda') + + qf = q[:, :, 0].float() + kf = k[:, :, 0].float() + scale = 1.0 / math.sqrt(hd) + attn = qf @ kf.T * scale + attn = torch.softmax(attn, dim=-1) + ref = attn @ v.float() + + mQ = ct.from_dlpack(q).mark_layout_dynamic(leading_dim=ct.get_leading_dim(q)) + mK = ct.from_dlpack(k).mark_layout_dynamic(leading_dim=ct.get_leading_dim(k)) + mV = ct.from_dlpack(v_kernel).mark_layout_dynamic(leading_dim=ct.get_leading_dim(v_kernel)) + mC = ct.from_dlpack(c).mark_layout_dynamic(leading_dim=ct.get_leading_dim(c)) + stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream) + + # Each n requires its own compiled kernel (s_k is compile-time). + kernel = FmhaV3StageCMulti(s_k=n) + print(f'n={n}: Compiling...', flush=True) + compiled = cute.compile(kernel, mQ, mK, mV, mC, stream) + print(f'n={n}: tmem s0={kernel.tmem_s0_offset} p0={kernel.tmem_p0_offset} ' + f'o0={kernel.tmem_o0_offset} alloc={kernel.num_tmem_alloc_cols} ' + f'kv_tx_bytes={kernel.kv_tx_bytes}', flush=True) + compiled(mQ, mK, mV, mC, stream) + torch.cuda.synchronize() + + out = c[:, :, 0].float() + cos = torch.nn.functional.cosine_similarity( + out.flatten().unsqueeze(0), ref.flatten().unsqueeze(0) + ).item() + max_abs = (out - ref).abs().max().item() + n_tiles = n // 128 + print(f'FMHA Stage-C Multi n={n} ({n_tiles} kv tiles): ' + f'cos {cos:.6f} max_abs {max_abs:.4f} ' + f'{"PASS" if cos >= 0.99 else "FAIL"}') + if cos < 0.99: + print(f' out[0,:4]={out[0,:4].tolist()}') + print(f' ref[0,:4]={ref[0,:4].tolist()}') + + +if __name__ == '__main__': + test() \ No newline at end of file