diff --git a/tests/unit/test_d1_3_write_read.py b/tests/unit/test_d1_3_write_read.py new file mode 100644 index 00000000..cf79af6d --- /dev/null +++ b/tests/unit/test_d1_3_write_read.py @@ -0,0 +1,232 @@ +""" +D1.3 SMEM-P: Debug test that checks if P written to SMEM is read back correctly. +Creates a simple test kernel that: +1. Writes known values to sP via coordinate indexing +2. Reads them back via pv_mma.make_fragment_A(sP) +3. Compares the values +""" +import torch, math +import cutlass, cutlass.cute as cute, cutlass.utils as utils +from cutlass.cute.nvgpu import tcgen05, cpasync +from cutlass import Float32, BFloat16, Int32, const_expr +from cutlass.utils import LayoutEnum +from cutlass.utils.tmem_allocator import find_tmem_tensor_col_offset +import cutlass.torch as ct +import cuda.bindings.driver as cuda + + +class SmemPWriteReadTest: + """Test kernel: write P to sP, read back, verify.""" + def __init__(self, head_dim=64, s_k=128): + self.head_dim = head_dim + self.s_k = s_k + self.pv_n_tile = min(head_dim, 256) + self.qk_mma_tiler = (128, 128, 128 * 4) + self.pv_mma_tiler = (128, self.pv_n_tile, 128) + self.use_smem_p = True + self.normalize = True + self.acc_dtype = Float32 + self.qk_acc_dtype = Float32 + self.q_dtype = BFloat16 + self.o_dtype = BFloat16 + self.use_2cta_instrs = False + self.cta_group = tcgen05.CtaGroup.ONE + self.cluster_shape_mn = (1, 1) + self.epilogue_warp_id = (0, 1, 2, 3) + self.mma_warp_id = 4 + self.tma_warp_id = 5 + self.threads_per_cta = 192 + self.num_acc_stage = 1 + self.scale_softmax_log2 = 1.0 / math.sqrt(self.head_dim) * math.log2(math.e) + self.kv_stage = 2 + self.q_stage = 1 + self.num_c_stage = 2 + self.c_layout = LayoutEnum.ROW_MAJOR + self.tmem_p0_offset = -1 + self.tOrP0_offset = 0 + + @cute.jit + def __call__(self, q, k, v, c, stream): + self.a_major = LayoutEnum.from_tensor(q).mma_major_mode() + self.b_major = LayoutEnum.from_tensor(k).mma_major_mode() + v_fmha = cute.make_tensor( + v.iterator, + cute.make_layout( + (self.pv_n_tile, self.s_k, 1), + stride=(1, self.pv_n_tile, self.pv_n_tile * self.s_k), + ), + ) + self.v_major = LayoutEnum.from_tensor(v_fmha).mma_major_mode() + + qk_mma = utils.sm100.make_trivial_tiled_mma( + self.q_dtype, self.q_dtype, self.a_major, self.b_major, + self.qk_acc_dtype, self.cta_group, (128, 128), tcgen05.OperandSource.SMEM + ) + pv_a_major = cute.nvgpu.OperandMajorMode.K + pv_mma = utils.sm100.make_trivial_tiled_mma( + self.q_dtype, self.q_dtype, pv_a_major, self.v_major, + self.qk_acc_dtype, self.cta_group, (128, self.pv_n_tile), + tcgen05.OperandSource.SMEM + ) + + # Setup + qk_thr = qk_mma.get_slice(0) + qk_as = qk_thr.partition_shape_C(self.qk_mma_tiler[:2]) + tStS = qk_thr.make_fragment_C(qk_as) + pv_thr = pv_mma.get_slice(0) + pv_as = pv_thr.partition_shape_C(self.pv_mma_tiler[:2]) + tOtO = pv_thr.make_fragment_C(pv_as) + + self.tmem_s0_offset = 0 + self.tmem_o0_offset = 0 + s_cols = self.qk_mma_tiler[1] + o_cols = find_tmem_tensor_col_offset(tOtO) + total = max(s_cols, o_cols) + _n = 1 + while _n < total: + _n *= 2 + self.num_tmem_alloc_cols = _n + + p_smem_s = utils.sm100.make_smem_layout_a(pv_mma, self.pv_mma_tiler, self.q_dtype, 1) + q_smem_s = utils.sm100.make_smem_layout_a(qk_mma, self.qk_mma_tiler, self.q_dtype, self.q_stage) + k_smem_s = utils.sm100.make_smem_layout_b(qk_mma, self.qk_mma_tiler, self.q_dtype, self.kv_stage) + v_smem_s = utils.sm100.make_smem_layout_b(pv_mma, self.pv_mma_tiler, self.q_dtype, self.kv_stage) + c_smem_s = utils.sm100.make_smem_layout_epi(self.o_dtype, self.c_layout, (128, self.pv_n_tile), 2) + + q_s = cute.slice_(q_smem_s, (None, None, None, 0)) + k_s = cute.slice_(k_smem_s, (None, None, None, 0)) + v_s = cute.slice_(v_smem_s, (None, None, None, 0)) + cta = cute.size(qk_mma.thr_id.shape) + self.q_tx_bytes = cute.size_in_bytes(self.q_dtype, q_s) * cta + self.kv_tx_bytes = (cute.size_in_bytes(self.q_dtype, k_s) + cute.size_in_bytes(self.q_dtype, v_s)) * cta + + tma_q, mQ = cute.nvgpu.make_tiled_tma_atom_A( + utils.sm100.cluster_shape_to_tma_atom_A(self.cluster_shape_mn, qk_mma.thr_id), + q, q_s, self.qk_mma_tiler, qk_mma, (1, 1, 1, 1) + ) + tma_k, mK = cute.nvgpu.make_tiled_tma_atom_B( + utils.sm100.cluster_shape_to_tma_atom_B(self.cluster_shape_mn, qk_mma.thr_id), + k, k_s, self.qk_mma_tiler, qk_mma, (1, 1, 1, 1) + ) + tma_v, mV = cute.nvgpu.make_tiled_tma_atom_B( + utils.sm100.cluster_shape_to_tma_atom_B(self.cluster_shape_mn, pv_mma.thr_id), + v_fmha, v_s, self.pv_mma_tiler, pv_mma, (1, 1, 1, 1) + ) + epi_s = cute.select(c_smem_s, mode=[0, 1]) + tma_c, mC = cpasync.make_tiled_tma_atom(cpasync.CopyBulkTensorTileS2GOp(), c, epi_s, (128, self.pv_n_tile)) + + self._kernel(qk_mma, pv_mma, tma_q, mQ, tma_k, mK, tma_v, mV, tma_c, mC, + p_smem_s, q_smem_s, k_smem_s, v_smem_s, c_smem_s, + tStS, tOtO, qk_thr, pv_thr).launch( + grid=(1, 1, 1), block=[self.threads_per_cta, 1, 1], stream=stream + ) + + @cute.kernel + def _kernel(self, qk_mma, pv_mma, tma_q, mQ, tma_k, mK, tma_v, mV, tma_c, mC, + p_smem_s, q_smem_s, k_smem_s, v_smem_s, c_smem_s, + tStS, tOtO, qk_thr, pv_thr): + tidx, _, _ = cute.arch.thread_idx() + warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx()) + + @cute.struct + class SS: + q_bar: cute.struct.MemRange[cutlass.Int64, self.q_stage * 2] + kv_bar: cute.struct.MemRange[cutlass.Int64, self.kv_stage * 2] + s_bar: cute.struct.MemRange[cutlass.Int64, 2] + acc_bar: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage * 2] + tmem_dealloc: cutlass.Int64 + holding: cutlass.Int32 + smem = utils.SmemAllocator() + st = smem.allocate(SS) + + sQ = smem.allocate_tensor(element_type=self.q_dtype, layout=q_smem_s.outer, byte_alignment=128, swizzle=q_smem_s.inner) + sK = smem.allocate_tensor(element_type=self.q_dtype, layout=k_smem_s.outer, byte_alignment=128, swizzle=k_smem_s.inner) + sV = smem.allocate_tensor(element_type=self.q_dtype, layout=v_smem_s.outer, byte_alignment=128, swizzle=v_smem_s.inner) + sP = smem.allocate_tensor(element_type=self.q_dtype, layout=p_smem_s.outer, byte_alignment=128, swizzle=p_smem_s.inner) + + # Only use softmax warps for this test + if warp_idx < 4: + # TMEM load partition for getting coordinates + tmem_load_atom = cute.make_copy_atom(tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)), self.qk_acc_dtype) + tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tStS) + + sfw_idx = tidx % (32 * len(self.epilogue_warp_id)) + thr_load = tiled_tmem_load.get_slice(sfw_idx) + tTMEM_LOADtS = thr_load.partition_S(tStS) + + cS = cute.make_identity_tensor((self.qk_mma_tiler[0], self.qk_mma_tiler[1])) + tScS = qk_thr.partition_C(cS) + tTMEM_LOADcS = thr_load.partition_D(tScS) + + # Write known values to sP: value = m * 128 + k (the linear index) + # Each thread writes its portion using coordinate indexing + sP_stage = sP[(None, None, None, 0)] + + # PRINT: coordinates for thread 0 + if sfw_idx == 0: + print(f"=== SMEM-P Write/Read Test ===") + print(f"sP shape: {cute.shape(sP)}") + print(f"sP_stage shape: {cute.shape(sP_stage)}") + print(f"sP_stage layout: {sP_stage.layout}") + print(f"tTMEM_LOADcS shape: {cute.shape(tTMEM_LOADcS)}") + print(f"tTMEM_LOADcS layout: {tTMEM_LOADcS.layout}") + + # Print first few coordinates for thread 0 + for j0 in range(4): + for j1 in range(4): + coord = tTMEM_LOADcS[(j0, 0), j1, 0, 0] + print(f" cS[{j0}, {j1}]: coord={coord}") + + # Write P values to SMEM + for j0 in range(32): + for j1 in range(4): + coord = tTMEM_LOADcS[(j0, 0), j1, 0, 0] + m_c = coord[0] + k_c = coord[1] + k0 = k_c % 16 + k1 = (k_c // 16) % 4 + k2 = k_c // 64 + # Write a known pattern: BF16(m_c * 128 + k_c) + # Use a simple value that's easy to verify + _val = BFloat16(1.0) # Just write 1.0 everywhere + sP_stage[(m_c, k0), 0, (k1, k2)] = _val + + cute.arch.fence_proxy("async.shared", space="cta") + + # Now read back via PV MMA's fragment + tCrP = pv_mma.make_fragment_A(sP) + + if sfw_idx == 0: + print(f"tCrP shape: {cute.shape(tCrP)}") + print(f"tCrP layout: {tCrP.layout}") + # Print first few values read back + for i in range(min(4, cute.size(tCrP, mode=[2]))): + print(f" tCrP[0,0,{i},0] = {tCrP[0, 0, i, 0]}") + + +def test_smem_p_write_read(): + hd = 64 + q = torch.randn(128, hd, 1, dtype=torch.bfloat16, device='cuda') + k = torch.randn(128, hd, 1, dtype=torch.bfloat16, device='cuda') + v = torch.randn(128, hd, dtype=torch.bfloat16, device='cuda') + c = torch.zeros(128, hd, 1, dtype=torch.bfloat16, device='cuda') + + kern = SmemPWriteReadTest(head_dim=hd, s_k=128) + stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream) + + v_tile = v.unsqueeze(-1) + mQ = ct.from_dlpack(q).mark_layout_dynamic(leading_dim=ct.get_leading_dim(q)) + mK = ct.from_dlpack(k).mark_layout_dynamic(leading_dim=ct.get_leading_dim(k)) + mV = ct.from_dlpack(v_tile).mark_layout_dynamic(leading_dim=ct.get_leading_dim(v_tile)) + mC = ct.from_dlpack(c).mark_layout_dynamic(leading_dim=ct.get_leading_dim(c)) + + print('Compiling...', flush=True) + compiled = cute.compile(kern, mQ, mK, mV, mC, stream) + print('Running...', flush=True) + compiled(mQ, mK, mV, mC, stream) + torch.cuda.synchronize() + print('Done.') + + +if __name__ == '__main__': + test_smem_p_write_read()