From a7e8b483cdae5c3d8faf4a34775032f322795a59 Mon Sep 17 00:00:00 2001 From: biondizzle Date: Thu, 28 May 2026 12:54:57 +0000 Subject: [PATCH] test: HD=64 multi-K-tile with correct source stride in SMEM writes --- tests/unit/test_umma_qk_hd64.cu | 195 ++++++++++++++++++++------------ 1 file changed, 125 insertions(+), 70 deletions(-) diff --git a/tests/unit/test_umma_qk_hd64.cu b/tests/unit/test_umma_qk_hd64.cu index 85a025c9..783a5768 100644 --- a/tests/unit/test_umma_qk_hd64.cu +++ b/tests/unit/test_umma_qk_hd64.cu @@ -1,6 +1,15 @@ /** - * UMMA QK GEMM Test — HD=64, debug: exact copy of working HD=16 pattern - * Only uses first 16 dims. If this fails, the issue is in SMEM/alignment. + * UMMA QK GEMM Test — HD=64 (4 K-tiles) + * + * Full multi-K-tile QK GEMM with proper SMEM writes. + * Key fix: source data stride ≠ SMEM tile width — must write manually. + * + * Pipeline: + * 1. Load Q (1, 64) into (128, 64) canonical SMEM + * 2. Load K (128, 64) into (128, 64) canonical SMEM + * 3. For each K-tile (16 BF16): construct offset descriptor, call MMA with accumulate + * 4. Read S from TMEM, apply 1/sqrt(HD) scale + * 5. Compare against scalar reference */ #include @@ -15,70 +24,102 @@ using namespace dsv4::kernels::attention; static bf16_t f32_to_bf16_host(float f) { uint32_t u; memcpy(&u,&f,4); return (uint16_t)(u>>16); } -static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; memcpy(&f,&u,4); return f; } + +constexpr int HD = 64; +constexpr int SK = 128; +constexpr int NKT = HD / MMA_K_BF16; // 4 +constexpr int BLOCK_MN = 128; + +/** + * Write Q (1, SRC_HD) into (128, SMEM_HD) canonical layout. + * Only row 0 has data. Source stride = SRC_HD, SMEM cols = SMEM_HD. + */ +template +__device__ void write_q_canonical(bf16_t* dst, const bf16_t* q) { + constexpr int CORES_MN = 128 / 8; // 16 + constexpr int CORES_K = SMEM_HD / 8; + // Zero all + for (int i = threadIdx.x; i < 128 * SMEM_HD; i += 128) dst[i] = 0; + // Row 0 only: core_mn=0, local_r=0 + for (int c = threadIdx.x; c < SRC_HD; c += 128) { + int ck = c / 8, lc = c % 8; + dst[ck * CORES_MN * 64 + lc] = q[c]; + } +} + +/** + * Write K (SK, SRC_HD) into (128, SMEM_HD) canonical layout. + * Source stride = SRC_HD, SMEM cols = SMEM_HD. + */ +template +__device__ void write_k_canonical(bf16_t* dst, const bf16_t* k) { + constexpr int CORES_MN = 128 / 8; // 16 + // Zero all + for (int i = threadIdx.x; i < 128 * SMEM_HD; i += 128) dst[i] = 0; + // Write actual rows + for (int i = threadIdx.x; i < SK_VAL * SMEM_HD; i += 128) { + int r = i / SMEM_HD; + int c = i % SMEM_HD; + if (r >= SK_VAL || c >= SRC_HD) continue; + int ck = c / 8, lc = c % 8; + int tmn = r / 8, lr = r % 8; + dst[ck * CORES_MN * 64 + tmn * 64 + lr * 8 + lc] = k[r * SRC_HD + c]; + } +} __global__ void __launch_bounds__(128) -test_umma_hd64_debug(const bf16_t* __restrict__ q, const bf16_t* __restrict__ k, +test_umma_hd64(const bf16_t* __restrict__ q, const bf16_t* __restrict__ k, float* __restrict__ s_out, float* __restrict__ s_scalar, float scale) { const int tid = threadIdx.x; - const int wid = tid / 32, lane = tid % 32; + const int wid = tid / WARP, lane = tid % WARP; - // EXACT same layout as test_umma_qk.cu (working HD=16 test) extern __shared__ char sbuf[]; uint32_t* sTmemBase = (uint32_t*)sbuf; bf16_t* sQ = (bf16_t*)(((uintptr_t)(sbuf + 4) + 15) & ~(uintptr_t)15); - bf16_t* sK = sQ + 128 * 16 + 4096; // Same padding as HD=16 test - float* sQ_row = (float*)(sK + 128 * 16); + bf16_t* sK = sQ + 128 * HD; // (128, 64) each = 16384 bytes - // Load first 16 dims of Q to SMEM + sQ_row for scalar - for (int d = tid; d < 16; d += 128) sQ_row[d] = bf16_to_f32(q[d]); + // Load Q (1, 64) → (128, 64) canonical + write_q_canonical(sQ, q); + // Load K (128, 64) → (128, 64) canonical + write_k_canonical(sK, k); + __syncthreads(); - // TMEM alloc (128 cols) — same as HD=16 test + // TMEM alloc — 128 columns for (128, 128) Layout D output if (wid == 1) { tmem_alloc(__cvta_generic_to_shared(sTmemBase), 128); } __syncthreads(); uint32_t tb = *sTmemBase; - // Load Q (first 16 dims) into (128, 16) canonical — manual write - // Zero sQ - for (int i = tid; i < 128 * 16; i += 128) sQ[i] = 0; - // Q row 0, first 16 dims - for (int c = tid; c < 16; c += 128) { - int ck = c / 8, lc = c % 8; - sQ[ck * 16 * 64 + lc] = q[c]; - } - - // Load K (first 16 cols of (128, 64)) into (128, 16) canonical - // K source stride is 64, but we only write 16 columns to SMEM - for (int i = tid; i < 128 * 16; i += 128) sK[i] = 0; - for (int r = 0; r < 128; r++) { - for (int c = tid; c < 16; c += 128) { - int ck = c / 8, lc = c % 8; - int tmn = r / 8, lr = r % 8; - sK[ck * 16 * 64 + tmn * 64 + lr * 8 + lc] = k[r * 64 + c]; - } - } - bf16_t* sQ_pad = sQ + 128 * 16; - for (int i = tid; i < 4096; i += 128) sQ_pad[i] = 0; - __syncthreads(); - - // Construct descriptors — EXACT same as HD=16 test + // Multi-K-tile QK GEMM uint32_t sQ_smem = __cvta_generic_to_shared(sQ); uint32_t sK_smem = __cvta_generic_to_shared(sK); - uint64_t desc_q = make_umma_desc_kmajor_none(sQ_smem, 128); - uint64_t desc_k = make_umma_desc_kmajor_none(sK_smem, 128); - uint32_t idesc = make_idesc(128, 128); + uint32_t idesc = make_idesc(BLOCK_MN, BLOCK_MN); - // MMA — 4 warp leaders call simultaneously (same as HD=16 test) - if (lane == 0) { - umma_ss_f16(tb, desc_q, desc_k, idesc, false); + for (int kt = 0; kt < NKT; kt++) { + // K-tile offset in canonical layout: + // Each 16-BF16 K-tile spans 2 core columns. + // Core column 2*kt starts at offset 2*kt * (128/8 * 128) bytes = 2*kt * 2048 bytes = kt * 4096 bytes. + uint32_t q_addr = sQ_smem + kt * BLOCK_MN * 32; + uint32_t k_addr = sK_smem + kt * BLOCK_MN * 32; + + uint64_t dq = make_umma_desc_kmajor_none(q_addr, BLOCK_MN); + uint64_t dk = make_umma_desc_kmajor_none(k_addr, BLOCK_MN); + + // 4 warp leaders call MMA (same as working HD=16 test) + if (lane == 0) { + umma_ss_f16(tb, dq, dk, idesc, kt > 0); + } + asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory"); + __syncthreads(); } + + // Final fence before TMEM read asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory"); __syncthreads(); - // Read from TMEM using Layout D — same as HD=16 test + // Read S from TMEM (Layout D: 32x32b.x8) for (int n = 0; n < 128 / 8; n++) { const int row = wid * 32; const int col = n * 8; @@ -88,36 +129,37 @@ test_umma_hd64_debug(const bf16_t* __restrict__ q, const bf16_t* __restrict__ k, asm volatile("tcgen05.wait::ld.sync.aligned;"); int out_row = wid * 32 + lane; - if (n < 1 && out_row < 128) { + if (out_row < SK) { for (int c = 0; c < 8; c++) { - s_out[out_row * 8 + c] = tmp[c] * scale; + int out_col = n * 8 + c; + if (out_col < SK) { + s_out[out_row * SK + out_col] = tmp[c] * scale; + } } } } __syncthreads(); - // Scalar reference — first 16 dims only + // Scalar reference if (tid == 0) { - for (int c = 0; c < 128; c++) { + for (int j = 0; j < SK; j++) { float dot = 0.0f; - for (int d = 0; d < 16; d++) - dot += sQ_row[d] * bf16_to_f32(k[c * 64 + d]); // k has stride 64 - s_scalar[c] = dot * scale; + for (int d = 0; d < HD; d++) + dot += bf16_to_f32(q[d]) * bf16_to_f32(k[j * HD + d]); + s_scalar[j] = dot * scale; } } - __syncthreads(); if (wid == 0) tmem_dealloc(tb, 128); } int main() { - printf("=== UMMA QK HD=64 DEBUG (exact HD=16 pattern, first 16 dims) ===\n"); - const int HD = 64, SK = 128; + printf("=== UMMA QK GEMM HD=64 (4 K-tiles, fixed stride) ===\n"); const float SCALE = 1.0f / sqrtf((float)HD); bf16_t* h_q = (bf16_t*)malloc(HD * sizeof(bf16_t)); bf16_t* h_k = (bf16_t*)malloc(SK * HD * sizeof(bf16_t)); - float* h_s_out = (float*)calloc(128*8, sizeof(float)); + float* h_s_out = (float*)calloc(SK * SK, sizeof(float)); float* h_s_scalar = (float*)calloc(SK, sizeof(float)); srand(42); @@ -126,35 +168,48 @@ int main() { bf16_t *d_q, *d_k; float *d_s_out, *d_s_scalar; cudaMalloc(&d_q, HD*sizeof(bf16_t)); cudaMalloc(&d_k, SK*HD*sizeof(bf16_t)); - cudaMalloc(&d_s_out, 128*8*sizeof(float)); cudaMalloc(&d_s_scalar, SK*sizeof(float)); + cudaMalloc(&d_s_out, SK*SK*sizeof(float)); cudaMalloc(&d_s_scalar, SK*sizeof(float)); cudaMemcpy(d_q, h_q, HD*sizeof(bf16_t), cudaMemcpyHostToDevice); cudaMemcpy(d_k, h_k, SK*HD*sizeof(bf16_t), cudaMemcpyHostToDevice); - int smem = (4 + 16 + 128*16*2 + 4096*2 + 128*16*2 + 16*4 + 256 + 127) & ~127; - test_umma_hd64_debug<<<1, 128, smem>>>(d_q, d_k, d_s_out, d_s_scalar, SCALE); + int smem = (4 + 16 + 2 * 128 * HD * sizeof(bf16_t) + 256 + 127) & ~127; + printf("SMEM: %d bytes (%d KB)\n", smem, smem / 1024); + + test_umma_hd64<<<1, 128, smem>>>(d_q, d_k, d_s_out, d_s_scalar, SCALE); cudaError_t err = cudaDeviceSynchronize(); if (err != cudaSuccess) { printf("CUDA ERROR: %s\n", cudaGetErrorString(err)); return 1; } - cudaMemcpy(h_s_out, d_s_out, 128*8*sizeof(float), cudaMemcpyDeviceToHost); + cudaMemcpy(h_s_out, d_s_out, SK*SK*sizeof(float), cudaMemcpyDeviceToHost); cudaMemcpy(h_s_scalar, d_s_scalar, SK*sizeof(float), cudaMemcpyDeviceToHost); - printf("Row 0 (MMA): "); - for (int c = 0; c < 8; c++) printf("%.6f ", h_s_out[0*8+c]); - printf("\nRow 0 scalar: "); - for (int c = 0; c < 8; c++) printf("%.6f ", h_s_scalar[c]); - printf("\n"); + printf("S[0,0..7] MMA: "); for(int c=0;c<8;c++) printf("%.6f ",h_s_out[0*SK+c]); printf("\n"); + printf("S[0,0..7] ref: "); for(int c=0;c<8;c++) printf("%.6f ",h_s_scalar[c]); printf("\n"); + printf("S[0,64..71] MMA: "); for(int c=64;c<72;c++) printf("%.6f ",h_s_out[0*SK+c]); printf("\n"); + printf("S[0,64..71] ref: "); for(int c=64;c<72;c++) printf("%.6f ",h_s_scalar[c]); printf("\n"); - float row0_max_diff = 0.0f, row0_max_val = 0.0f; - for (int c = 0; c < 8; c++) { - row0_max_diff = fmaxf(row0_max_diff, fabsf(h_s_out[0*8+c] - h_s_scalar[c])); - row0_max_val = fmaxf(row0_max_val, fabsf(h_s_scalar[c])); + float max_diff = 0.0f, max_val = 0.0f; + for (int c = 0; c < SK; c++) { + float diff = fabsf(h_s_out[0*SK+c] - h_s_scalar[c]); + max_diff = fmaxf(max_diff, diff); + max_val = fmaxf(max_val, fabsf(h_s_scalar[c])); } - float row0_rel = row0_max_val > 0 ? row0_max_diff / row0_max_val : row0_max_diff; - printf("Row 0 rel err: %.8f\n", row0_rel); - printf("Test %s\n", row0_rel < 0.001f ? "PASSED" : "FAILED"); + float rel_err = max_val > 0 ? max_diff / max_val : max_diff; + printf("Row 0 rel err (128 cols): %.8f\n", rel_err); + + float max_nonzero = 0.0f; + for (int r = 1; r < SK; r++) + for (int c = 0; c < SK; c++) + max_nonzero = fmaxf(max_nonzero, fabsf(h_s_out[r*SK+c])); + printf("Rows 1-127 max abs: %.8f\n", max_nonzero); + + bool row0_ok = rel_err < 0.01f; + bool rows_zero = max_nonzero < 1e-4f; + printf("Row 0: %s | Rows 1-127 zero: %s\n", + row0_ok ? "PASS" : "FAIL", rows_zero ? "PASS" : "FAIL"); + printf("Overall: %s\n", (row0_ok && rows_zero) ? "PASSED" : "FAILED"); cudaFree(d_q); cudaFree(d_k); cudaFree(d_s_out); cudaFree(d_s_scalar); free(h_q); free(h_k); free(h_s_out); free(h_s_scalar); - return row0_rel < 0.001f ? 0 : 1; + return (row0_ok && rows_zero) ? 0 : 1; }