diff --git a/tests/unit/test_fmha_hd64_n16_v2.cu b/tests/unit/test_fmha_hd64_n16_v2.cu
new file mode 100644
index 00000000..bdf6d756
--- /dev/null
+++ b/tests/unit/test_fmha_hd64_n16_v2.cu
@@ -0,0 +1,260 @@
+/**
+ * Full FMHA HD=64 with PV via SS MMA, using N=16 sub-tiles (4 per K-tile).
+ * This avoids the N=64 Layout D bug where TMEM columns 32-35 and 48-51 are missing.
+ * 
+ * Each PV sub-tile: P(128,16) × V(16,16) → O(128,16) at TMEM offset d/8*8
+ * 4 sub-tiles cover d=0..63
+ */
+
+#include <cuda_runtime.h>
+#include <cstdio>
+#include <cmath>
+#include <cstdlib>
+#include <cstring>
+
+#include "dsv4/kernels/attention/fmha_common.cuh"
+#include "dsv4/kernels/attention/fmha_umma_desc.cuh"
+
+using namespace dsv4::kernels::attention;
+
+static bf16_t f32_to_bf16_host(float f) { uint32_t u; memcpy(&u,&f,4); return (uint16_t)(u>>16); }
+static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; memcpy(&f,&u,4); return f; }
+
+constexpr int HD = 64, SK = 128, BLOCK_MN = 128;
+constexpr int NKT_QK = HD / MMA_K_BF16;     // 4
+constexpr int NKT_PV = SK / MMA_K_BF16;     // 8
+constexpr int TILE_SZ = BLOCK_MN * MMA_K_BF16;  // 2048 BF16
+// V sub-tile: (16, 16) canonical with BLOCK_MN=16
+// CORES_MN = 16/8 = 2, CORES_K = 2
+// 2 * 2 * 64 = 256 BF16 per V sub-tile
+constexpr int V_SUB_TILE_SZ = 256;  // BF16
+
+__global__ void __launch_bounds__(128)
+test_fmha_hd64_n16(const bf16_t* q, const bf16_t* k, const bf16_t* v,
+                    bf16_t* o_out, float* o_scalar, float scale)
+{
+    const int tid = threadIdx.x, wid = tid / 32, lane = tid % 32;
+
+    extern __shared__ char sbuf[];
+    uint32_t* sTmemBase = (uint32_t*)sbuf;
+    bf16_t* sQ0 = (bf16_t*)(((uintptr_t)(sbuf + 4) + 15) & ~(uintptr_t)15);
+    bf16_t* sK0 = sQ0 + NKT_QK * TILE_SZ;
+    bf16_t* sPk = (bf16_t*)(((uintptr_t)(sK0 + NKT_QK * TILE_SZ) + 127) & ~(uintptr_t)127);
+    bf16_t* sV = (bf16_t*)(((uintptr_t)(sPk + TILE_SZ) + 127) & ~(uintptr_t)127);
+    float* s_p_vals = (float*)(sV + NKT_PV * V_SUB_TILE_SZ);  // Only 1 V sub-tile at a time
+
+    // Load Q K-tiles (4 × (128,16) canonical)
+    for (int kt = 0; kt < NKT_QK; kt++) {
+        bf16_t* sq = sQ0 + kt * TILE_SZ;
+        for (int i = tid; i < TILE_SZ; i += 128) sq[i] = 0;
+        for (int d = tid; d < MMA_K_BF16; d += 128) {
+            int ck = d / 8, lc = d % 8;
+            sq[ck * 16 * 64 + lc] = q[kt * MMA_K_BF16 + d];
+        }
+    }
+
+    // Load K K-tiles (4 × (128,16) canonical)
+    for (int kt = 0; kt < NKT_QK; kt++) {
+        bf16_t* sk = sK0 + kt * TILE_SZ;
+        for (int i = tid; i < TILE_SZ; i += 128) sk[i] = 0;
+        for (int r = 0; r < SK; r++) {
+            for (int d = tid; d < MMA_K_BF16; d += 128) {
+                int ck = d / 8, lc = d % 8;
+                int tmn = r / 8, lr = r % 8;
+                sk[ck * 16 * 64 + tmn * 64 + lr * 8 + lc] = k[r * HD + kt * MMA_K_BF16 + d];
+            }
+        }
+    }
+
+    // NOTE: We load V sub-tiles on-the-fly in the PV loop (only need 1 sub-tile at a time)
+    __syncthreads();
+
+    // TMEM alloc: 128 columns
+    if (wid == 1) tmem_alloc(__cvta_generic_to_shared(sTmemBase), 128);
+    __syncthreads();
+    uint32_t tb = *sTmemBase;
+
+    // ===== QK GEMM (4 K-tiles) =====
+    {
+        uint32_t idesc = make_idesc(BLOCK_MN, BLOCK_MN);
+        for (int kt = 0; kt < NKT_QK; kt++) {
+            bf16_t* sq = sQ0 + kt * TILE_SZ;
+            bf16_t* sk = sK0 + kt * TILE_SZ;
+            uint64_t dq = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sq), BLOCK_MN);
+            uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sk), BLOCK_MN);
+            if (tid == 0) umma_ss_f16(tb, dq, dk, idesc, kt > 0);
+            asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
+            __syncthreads();
+        }
+    }
+
+    // ===== Softmax (warp 0, row 0 only) =====
+    if (wid == 0) {
+        float s_vals[SK], row_max = -INFINITY;
+        for (int n = 0; n < SK / 8; n++) {
+            float tmp[8];
+            asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
+                : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
+                  "=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
+                : "r"(tb + n*8));
+            asm volatile("tcgen05.wait::ld.sync.aligned;");
+            if (lane == 0) for (int c=0;c<8;c++) {
+                s_vals[n*8+c] = tmp[c] * scale;
+                row_max = fmaxf(row_max, tmp[c] * scale);
+            }
+        }
+        row_max = wmax(row_max);
+        float row_sum = 0.0f;
+        if (lane == 0) for (int j=0;j<SK;j++) {
+            s_vals[j] = expf(s_vals[j] - row_max);
+            row_sum += s_vals[j];
+        }
+        row_sum = wsum(row_sum);
+        if (lane == 0) for (int j=0;j<SK;j++) s_vals[j] /= row_sum;
+        if (lane == 0) for (int j=0;j<SK;j++) s_p_vals[j] = s_vals[j];
+    }
+    __syncthreads();
+
+    // ===== PV GEMM: N=16 sub-tiles, 4 per K-tile =====
+    // For each K-tile (j=0..7), for each N-sub-tile (n=0..3):
+    //   P(128,16) × V(n*16..n*16+15, 16) → O(128,16) at TMEM tb + n*16
+    //
+    // V sub-tile n has dimensions (16, 16) with BLOCK_MN=16
+    // V[d][j] where d = n*16 + dd (dd=0..15), j = kt*16 + lr (lr=0..15)
+    // Canonical layout for (16, 16): CORES_MN=2, CORES_K=2
+    // core(g_mn, g_k) at g_k * 2 * 64 + g_mn * 64 + local_r * 8 + local_c
+
+    {
+        uint32_t idesc_pv16 = make_idesc(BLOCK_MN, 16);  // (128, 16) — proven at HD=16
+        uint64_t dp = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sPk), BLOCK_MN);
+
+        for (int n = 0; n < HD / 16; n++) {  // 4 N-sub-tiles
+            int d_base = n * 16;
+
+            for (int kt = 0; kt < NKT_PV; kt++) {  // 8 K-tiles
+                // Fill sPk from s_p_vals for this K-tile
+                for (int i = tid; i < TILE_SZ; i += 128) sPk[i] = 0;
+                if (tid < 16) {
+                    int c = tid;
+                    int ck = c / 8, lc = c % 8;
+                    sPk[ck * 16 * 64 + 0 * 64 + 0 * 8 + lc] = f32_to_bf16(s_p_vals[kt * MMA_K_BF16 + c]);
+                }
+
+                // Load V sub-tile n for K-tile kt
+                // V[d_base+dd, kt*16+lr] in GMEM: v[(d_base+dd) * SK + kt*16 + lr]
+                // Canonical for (16, 16): CORES_MN=2, CORES_K=2
+                for (int i = tid; i < V_SUB_TILE_SZ; i += 128) sV[i] = 0;
+                for (int dd = tid; dd < 16; dd += 128) {
+                    for (int lr = 0; lr < MMA_K_BF16; lr++) {
+                        int r = kt * MMA_K_BF16 + lr;
+                        int g_mn = dd / 8, g_k = lr / 8;
+                        int llr = dd % 8, lc = lr % 8;
+                        // (16, 16) canonical: CORES_MN=2
+                        sV[g_k * 2 * 64 + g_mn * 64 + llr * 8 + lc] = v[(d_base + dd) * SK + r];
+                    }
+                }
+                __syncthreads();
+
+                // PV MMA: P(128,16) × V(16,16) → O(128,16) at TMEM offset n*16
+                uint64_t dv = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sV), 16);
+                bool accumulate = (kt > 0);  // First K-tile: overwrite, rest: accumulate
+                if (tid == 0) umma_ss_f16(tb + n * 16, dp, dv, idesc_pv16, accumulate);
+                asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
+                __syncthreads();
+            }
+        }
+    }
+
+    // ===== Epilogue: read O from TMEM =====
+    if (wid == 0) {
+        float o_vals[HD];
+        for (int n = 0; n < HD / 8; n++) {
+            float tmp[8];
+            asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
+                : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
+                  "=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
+                : "r"(tb + n*8));
+            asm volatile("tcgen05.wait::ld.sync.aligned;");
+            if (lane == 0) for (int c=0;c<8;c++) o_vals[n*8+c] = tmp[c];
+        }
+        if (lane == 0) for (int d=0;d<HD;d++) o_out[d] = f32_to_bf16(o_vals[d]);
+    }
+    __syncthreads();
+
+    // Scalar reference
+    if (tid == 0) {
+        float s[SK];
+        for (int j=0;j<SK;j++) {
+            float dot = 0.0f;
+            for (int d=0;d<HD;d++) dot += bf16_to_f32(q[d]) * bf16_to_f32(k[j*HD+d]);
+            s[j] = dot * scale;
+        }
+        float mx = -INFINITY;
+        for (int j=0;j<SK;j++) mx = fmaxf(mx, s[j]);
+        float sm = 0.0f;
+        for (int j=0;j<SK;j++) { s[j] = expf(s[j]-mx); sm += s[j]; }
+        for (int j=0;j<SK;j++) s[j] /= sm;
+        for (int d=0;d<HD;d++) {
+            float ov = 0.0f;
+            for (int j=0;j<SK;j++) ov += s[j] * bf16_to_f32(v[d*SK+j]);
+            o_scalar[d] = ov;
+        }
+    }
+
+    if (wid == 0) tmem_dealloc(tb, 128);
+}
+
+int main() {
+    printf("=== Full FMHA HD=64 with N=16 PV sub-tiles ===\n");
+    const float SCALE = 1.0f / sqrtf((float)HD);
+
+    bf16_t* h_q = (bf16_t*)malloc(HD*sizeof(bf16_t));
+    bf16_t* h_k = (bf16_t*)malloc(SK*HD*sizeof(bf16_t));
+    bf16_t* h_v = (bf16_t*)malloc(HD*SK*sizeof(bf16_t));
+    bf16_t* h_o = (bf16_t*)calloc(HD, sizeof(bf16_t));
+    float* h_o_scalar = (float*)calloc(HD, sizeof(float));
+
+    srand(42);
+    for (int d=0;d<HD;d++) h_q[d] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
+    for (int i=0;i<SK*HD;i++) h_k[i] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
+    for (int i=0;i<HD*SK;i++) h_v[i] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
+
+    bf16_t *d_q,*d_k,*d_v,*d_o; float *d_o_scalar;
+    cudaMalloc(&d_q, HD*sizeof(bf16_t));
+    cudaMalloc(&d_k, SK*HD*sizeof(bf16_t));
+    cudaMalloc(&d_v, HD*SK*sizeof(bf16_t));
+    cudaMalloc(&d_o, HD*sizeof(bf16_t));
+    cudaMalloc(&d_o_scalar, HD*sizeof(float));
+    cudaMemcpy(d_q, h_q, HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
+    cudaMemcpy(d_k, h_k, SK*HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
+    cudaMemcpy(d_v, h_v, HD*SK*sizeof(bf16_t), cudaMemcpyHostToDevice);
+
+    int smem = (4+16 + NKT_QK*TILE_SZ*2 + NKT_QK*TILE_SZ*2 + TILE_SZ*2 + V_SUB_TILE_SZ*2 + SK*4 + 256 + 127) & ~127;
+    printf("SMEM: %d bytes (%.1f KB)\n", smem, smem/1024.0f);
+    cudaFuncSetAttribute(test_fmha_hd64_n16, cudaFuncAttributeMaxDynamicSharedMemorySize, smem);
+    test_fmha_hd64_n16<<<1, 128, smem>>>(d_q, d_k, d_v, d_o, d_o_scalar, SCALE);
+
+    cudaError_t err = cudaDeviceSynchronize();
+    if (err != cudaSuccess) { printf("CUDA ERROR: %s\n", cudaGetErrorString(err)); return 1; }
+
+    cudaMemcpy(h_o, d_o, HD*sizeof(bf16_t), cudaMemcpyDeviceToHost);
+    cudaMemcpy(h_o_scalar, d_o_scalar, HD*sizeof(float), cudaMemcpyDeviceToHost);
+
+    printf("O[0..7] MMA:  "); for(int d=0;d<8;d++) printf("%.6f ",bf16_to_f32_host(h_o[d])); printf("\n");
+    printf("O[0..7] ref:  "); for(int d=0;d<8;d++) printf("%.6f ",h_o_scalar[d]); printf("\n");
+    printf("O[32..39] MMA: "); for(int d=32;d<40;d++) printf("%.6f ",bf16_to_f32_host(h_o[d])); printf("\n");
+    printf("O[32..39] ref: "); for(int d=32;d<40;d++) printf("%.6f ",h_o_scalar[d]); printf("\n");
+
+    float cs=0,na=0,nb=0;
+    for (int d=0;d<HD;d++) {
+        float a=bf16_to_f32_host(h_o[d]),b=h_o_scalar[d];
+        if(fabsf(b)>1e-4f) { cs+=a*b; na+=a*a; nb+=b*b; }
+    }
+    cs /= (sqrtf(na)*sqrtf(nb)+1e-10f);
+    printf("Filtered cosine: %.8f\n", cs);
+    printf("Test %s\n", cs > 0.999f ? "PASSED" : "FAILED");
+
+    cudaFree(d_q); cudaFree(d_k); cudaFree(d_v); cudaFree(d_o); cudaFree(d_o_scalar);
+    free(h_q); free(h_k); free(h_v); free(h_o); free(h_o_scalar);
+    return cs > 0.999f ? 0 : 1;
+}