/**
 * Test TMA-loaded QK GEMM only (no softmax, no PV, no epilogue).
 * Isolates: TMA load → canonical write → UMMA QK → TMEM read.
 * Compares against reference scalar dot product.
 */

#include <cuda_runtime.h>
#include <cuda.h>
#include <cstdio>
#include <cmath>
#include <cstdlib>
#include <cstring>

#ifndef HD_VAL
#define HD_VAL 64
#endif

#include "dsv4/kernels/attention/fmha_common.cuh"
#include "dsv4/kernels/attention/fmha_umma_desc.cuh"
#include "dsv4/kernels/attention/fmha_tma.cuh"

using namespace dsv4::kernels::attention;

static bf16_t f32_to_bf16_host(float f) { uint32_t u; memcpy(&u,&f,4); return (uint16_t)(u>>16); }
static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; memcpy(&f,&u,4); return f; }

constexpr int HD = HD_VAL;
constexpr int SK = 128;
constexpr int NKT = HD / MMA_K_BF16;

__global__ void __launch_bounds__(192)
test_qk_tma_kernel(
    float* __restrict__ out_s,      // (T, SK) — raw QK scores from TMEM
    CUtensorMap* __restrict__ tma_q,
    CUtensorMap* __restrict__ tma_k,
    int T, int s_k
) {
    static constexpr int TILE_SZ = 128 * MMA_K_BF16;
    static constexpr int TMEM_N = (HD <= 128) ? 128 : 256;
    static constexpr int NUM_READS = SK / 8;  // SK_TILE=128, 128/8=16 reads per row
    static constexpr int TMA_TILE_BYTES = 128 * MMA_K_BF16 * 2;

    const int tid = threadIdx.x;
    const int wid = tid / 32;
    const int lane = tid % 32;
    const bool is_softmax_warp = (wid < 4);
    const bool is_mma_warp = (wid == 4);
    const bool is_load_warp = (wid == 5);

    // SMEM
    extern __shared__ __align__(128) char sbuf[];
    size_t off = 0;
    uint32_t* sTmemBase = (uint32_t*)sbuf; off = 4;
    off = (off + 127) & ~(size_t)127;
    uint64_t* sMbar = (uint64_t*)(sbuf + off); off += 8;
    off = (off + 127) & ~(size_t)127;
    bf16_t* sTmaBuf = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
    off = (off + 127) & ~(size_t)127;
    bf16_t* sQ = (bf16_t*)(sbuf + off); off += 128 * HD * sizeof(bf16_t);
    off = (off + 127) & ~(size_t)127;
    bf16_t* sK = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);

    // Init
    if (tid == 0) {
        tma_mbarrier_init((uint32_t)__cvta_generic_to_shared(sMbar), 1);
        asm volatile("fence.mbarrier_init.release.cluster;" ::: "memory");
    }
    if (is_mma_warp) tmem_alloc(__cvta_generic_to_shared(sTmemBase), TMEM_N);
    __syncthreads();
    uint32_t tb = *sTmemBase;
    const uint32_t mbar_addr = (uint32_t)__cvta_generic_to_shared(sMbar);
    int phase = 0;

    // Load full Q (128, HD)
    if (is_load_warp) {
        for (int i = lane; i < 128 * HD; i += 32) sQ[i] = 0;
    }
    __syncthreads();

    for (int qkt = 0; qkt < NKT; qkt++) {
        if (is_load_warp && lane == 0) {
            tma_load_2d((uint32_t)__cvta_generic_to_shared(sTmaBuf), (uint64_t)tma_q, mbar_addr, qkt * MMA_K_BF16, 0);
            tma_mbarrier_arrive_expect_tx(mbar_addr, TMA_TILE_BYTES);
        }
        tma_mbarrier_wait(mbar_addr, phase); phase ^= 1;
        __syncthreads();

        if (is_load_warp) {
            constexpr int CORES_MN = 16;
            for (int i = lane; i < 128 * 16; i += 32) {
                int r = i / 16, c = i % 16;
                int core_mn = r / 8, local_r = r % 8;
                int core_k_sub = c / 8, local_c = c % 8;
                int core_k_full = qkt * 2 + core_k_sub;
                int dst_idx = core_k_full * CORES_MN * 64 + core_mn * 64 + local_r * 8 + local_c;
                sQ[dst_idx] = sTmaBuf[i];
            }
        }
        __syncthreads();
    }

    // QK GEMM: loop over K sub-tiles
    for (int kt = 0; kt < NKT; kt++) {
        if (is_load_warp && lane == 0) {
            tma_load_2d((uint32_t)__cvta_generic_to_shared(sTmaBuf), (uint64_t)tma_k, mbar_addr, kt * MMA_K_BF16, 0);
            tma_mbarrier_arrive_expect_tx(mbar_addr, TMA_TILE_BYTES);
        }
        tma_mbarrier_wait(mbar_addr, phase); phase ^= 1;
        __syncthreads();

        if (is_load_warp) write_smem_canonical<128, MMA_K_BF16, 32>(sK, sTmaBuf);
        __syncthreads();

        if (is_mma_warp) {
            uint32_t idesc = make_idesc(128, 128);
            uint32_t sq_kt = (uint32_t)__cvta_generic_to_shared(sQ) + kt * 128 * 32;
            uint64_t dq = make_umma_desc_kmajor_none(sq_kt, 128);
            uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK), 128);
            if (tid == 128) umma_ss_f16(tb, dq, dk, idesc, kt > 0);
            asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
        }
        __syncthreads();
    }

    asm volatile("fence.sc.gpu;" ::: "memory");
    __syncthreads();

    // Read S from TMEM, write to GMEM
    const bool my_warp_active = (T <= 32) ? (wid == 0) : is_softmax_warp;
    const int my_row = my_warp_active ? (wid * 32 + lane) : 0;
    const bool my_row_active = my_warp_active && (my_row < T);

    if (my_warp_active) {
        for (int n = 0; n < NUM_READS; n++) {
            float tmp[8];
            asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
                : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
                  "=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
                : "r"(tb + n * 8));
            asm volatile("tcgen05.wait::ld.sync.aligned;");
            if (my_row_active) {
                for (int c = 0; c < 8; c++) {
                    int col = n * 8 + c;
                    if (col < s_k) out_s[my_row * s_k + col] = tmp[c];
                }
            }
        }
    }
    __syncthreads();
    if (is_mma_warp) tmem_dealloc(tb, TMEM_N);
}

int main() {
    printf("TMA QK-Only Test (HD=%d, SK=%d)\n", HD, SK);
    const int T = 4;

    bf16_t* h_q = (bf16_t*)calloc(128 * HD, sizeof(bf16_t));
    bf16_t* h_k = (bf16_t*)calloc(SK * HD, sizeof(bf16_t));
    srand(42);
    for (int i = 0; i < T * HD; i++) h_q[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
    for (int i = 0; i < SK * HD; i++) h_k[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);

    bf16_t *d_q, *d_k; float *d_out;
    cudaMalloc(&d_q, 128 * HD * sizeof(bf16_t));
    cudaMalloc(&d_k, SK * HD * sizeof(bf16_t));
    cudaMalloc(&d_out, 128 * SK * sizeof(float));
    cudaMemcpy(d_q, h_q, 128 * HD * sizeof(bf16_t), cudaMemcpyHostToDevice);
    cudaMemcpy(d_k, h_k, SK * HD * sizeof(bf16_t), cudaMemcpyHostToDevice);

    CUtensorMap tma_q, tma_k;
    CUtensorMap *d_tma_q, *d_tma_k;
    create_tma_desc_2d_bf16(&tma_q, d_q, 128, HD, 128, 16);
    create_tma_desc_2d_bf16(&tma_k, d_k, SK, HD, 128, 16);
    cudaMalloc(&d_tma_q, sizeof(CUtensorMap));
    cudaMalloc(&d_tma_k, sizeof(CUtensorMap));
    cudaMemcpy(d_tma_q, &tma_q, sizeof(CUtensorMap), cudaMemcpyHostToDevice);
    cudaMemcpy(d_tma_k, &tma_k, sizeof(CUtensorMap), cudaMemcpyHostToDevice);

    int smem = 4 + 8 + 128*16*2 + 128*HD*2 + 128*16*2 + 4096;
    test_qk_tma_kernel<<<1, 192, smem>>>(d_out, d_tma_q, d_tma_k, T, SK);
    cudaError_t err = cudaDeviceSynchronize();
    if (err != cudaSuccess) { printf("CUDA ERROR: %s\n", cudaGetErrorString(err)); return 1; }

    float* h_out = (float*)malloc(128 * SK * sizeof(float));
    cudaMemcpy(h_out, d_out, 128 * SK * sizeof(float), cudaMemcpyDeviceToHost);

    // Reference: scalar QK
    float scale = 1.0f / sqrtf((float)HD);
    int fail = 0;
    float max_rel = 0;
    for (int t = 0; t < T; t++) {
        for (int j = 0; j < SK; j++) {
            float dot = 0;
            for (int d = 0; d < HD; d++)
                dot += bf16_to_f32_host(h_q[t * HD + d]) * bf16_to_f32_host(h_k[j * HD + d]);
            float ref = dot * scale;
            float got = h_out[t * SK + j];
            float rel = fabsf(ref) > 1e-4f ? fabsf(got - ref) / fabsf(ref) : fabsf(got - ref);
            if (rel > max_rel) max_rel = rel;
            if (rel > 0.01f && fail < 5) printf("  t=%d j=%d: ref=%.6f got=%.6f rel=%.4f\n", t, j, ref, got, rel);
            if (rel > 0.01f) fail++;
        }
    }
    printf("Max relative error: %.6f, failures: %d\n", max_rel, fail);
    printf("%s\n", fail == 0 ? "PASSED" : "FAILED");

    return fail == 0 ? 0 : 1;
}
