biondizzle
b3d1aae038
mxf4nvf4 requires BOTH A and B to be FP4 (E2M1 packed). Changes: - a_dtype_t: float_e4m3_t → float_e2m1_unpacksmem_t - UMMA_K: 32 → 64 (FP4 MMA atom) - L1 epilogue: FP8 quant → E2M1 FP4 quantization with nearest-neighbor - L1 output SMEM: packed E2M1 (2 per byte), TMA store uint8 - TMA descriptors: adjusted for FP4 packing (K/2 bytes per row) - SymmBuffer: uint8 activations, shape (M, K//2) - Staging kernel: BF16 → E2M1 packed + UE4M3 block16 scales
224 lines
10 KiB
C++
224 lines
10 KiB
C++
#pragma once
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#include <torch/python.h>
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#include "../../jit/compiler.hpp"
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#include "../../jit/kernel_runtime.hpp"
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#include "../../utils/exception.hpp"
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#include "../../utils/format.hpp"
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#include "runtime_utils.hpp"
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#include <deep_gemm/layout/mega_moe.cuh>
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#include <deep_gemm/layout/sym_buffer.cuh>
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#include "../heuristics/mega_moe.hpp"
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namespace deep_gemm {
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class SM100FP8NVFP4MegaMoERuntime final : public LaunchRuntime<SM100FP8NVFP4MegaMoERuntime> {
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public:
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struct Args {
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// Templated arguments
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int num_max_tokens_per_rank;
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int hidden, intermediate_hidden;
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int num_experts, num_topk;
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int num_ranks;
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float activation_clamp;
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bool fast_math;
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MegaMoEConfig config;
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// Runtime arguments
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void* y;
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int* cumulative_local_expert_recv_stats;
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int num_tokens;
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layout::SymBuffer<> sym_buffer_ptrs;
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// Tensormap
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CUtensorMap tensor_map_l1_acts;
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CUtensorMap tensor_map_l1_acts_sf;
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CUtensorMap tensor_map_l1_weights;
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CUtensorMap tensor_map_l1_weights_sf;
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CUtensorMap tensor_map_l1_output;
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CUtensorMap tensor_map_l2_acts;
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CUtensorMap tensor_map_l2_acts_sf;
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CUtensorMap tensor_map_l2_weights;
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CUtensorMap tensor_map_l2_weights_sf;
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// Launch configs
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LaunchArgs launch_args;
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};
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static std::string generate_impl(const Args& args) {
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return fmt::format(R"(
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#include <deep_gemm/impls/sm100_fp8_nvfp4_mega_moe.cuh>
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using namespace deep_gemm;
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static void __instantiate_kernel() {{
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auto ptr = reinterpret_cast<void*>(&sm100_fp8_nvfp4_mega_moe_impl<
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{},
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{}, {},
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{}, {},
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{},
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{}, {}, {},
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{},
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{}, {},
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{},
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{},
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{},
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{}, {}, {},
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{}, {},
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{},
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{}
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>);
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}};
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)", args.num_max_tokens_per_rank,
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args.hidden, args.intermediate_hidden,
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args.num_experts, args.num_topk,
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args.config.num_experts_per_wave,
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args.config.block_m, args.config.block_n, args.config.block_k,
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args.config.store_block_m,
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args.config.sf_block_m, args.config.sf_block_n,
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args.config.num_max_pool_tokens,
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args.config.num_padded_sf_pool_tokens,
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args.config.num_stages,
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args.config.num_dispatch_threads, args.config.num_non_epilogue_threads, args.config.num_epilogue_threads,
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args.launch_args.grid_dim.first, args.num_ranks,
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to_string(args.activation_clamp),
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args.fast_math ? "true" : "false");
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}
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static void launch_impl(const KernelHandle& kernel, const LaunchConfigHandle& config, Args args) {
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DG_CUDA_UNIFIED_CHECK(launch_kernel(kernel, config,
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args.y,
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args.cumulative_local_expert_recv_stats,
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args.num_tokens,
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args.sym_buffer_ptrs,
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args.tensor_map_l1_acts,
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args.tensor_map_l1_acts_sf,
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args.tensor_map_l1_weights,
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args.tensor_map_l1_weights_sf,
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args.tensor_map_l1_output,
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args.tensor_map_l2_acts,
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args.tensor_map_l2_acts_sf,
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args.tensor_map_l2_weights,
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args.tensor_map_l2_weights_sf
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));
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}
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};
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static void sm100_fp8_nvfp4_mega_moe(
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const torch::Tensor& y,
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const torch::Tensor& l1_acts, const torch::Tensor& l1_acts_sf,
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const torch::Tensor& l2_acts, const torch::Tensor& l2_acts_sf,
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const torch::Tensor& l1_weights, const torch::Tensor& l2_weights,
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const torch::Tensor& l1_weights_sf, const torch::Tensor& l2_weights_sf,
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const std::optional<torch::Tensor> cumulative_local_expert_recv_stats,
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const std::vector<int64_t>& sym_buffer_ptrs,
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const int& rank_idx, const int& num_max_tokens_per_rank,
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const int& num_experts_per_rank,
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const int& num_tokens, const int& num_topk,
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const int& hidden, const int& intermediate_hidden,
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const float& activation_clamp,
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const bool& fast_math
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) {
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const auto num_ranks = static_cast<int>(sym_buffer_ptrs.size());
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const auto num_experts = num_experts_per_rank * num_ranks;
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const auto num_padded_sf_pool_tokens = static_cast<int>(l1_acts_sf.size(0));
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// Heuristics
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const auto config = get_mega_moe_config(
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num_ranks, num_experts, num_experts_per_rank,
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num_max_tokens_per_rank, num_tokens, num_topk, hidden, intermediate_hidden, num_padded_sf_pool_tokens);
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// NVFP4: kGranK=16 for group_size=16
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constexpr int kGranK = 16;
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// Make tensormap — weight/activation TMA descriptors are the same as MXFP4
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// (E2M1 packed uint8 is the same format regardless of scale type)
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// NVFP4: activations are E2M1 packed uint8, so K-dim is hidden/2 bytes
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const auto tensor_map_l1_acts = make_tma_2d_desc(l1_acts,
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hidden / 2, config.num_max_pool_tokens,
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config.block_k / 2, config.load_block_m,
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static_cast<int>(l1_acts.stride(-2)),
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config.swizzle_acts_mode / 2);
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// NVFP4 SF TMA: kGranK=16, so SF K-dim is hidden/16, packed as hidden/64 int32
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const auto tensor_map_l1_acts_sf = make_tma_sf_desc(cute::UMMA::Major::MN, l1_acts_sf,
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config.num_padded_sf_pool_tokens, hidden,
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config.sf_block_m, kGranK,
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1, 0);
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const auto tensor_map_l1_weights = make_tma_2d_desc(l1_weights,
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hidden, num_experts_per_rank * intermediate_hidden * 2,
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config.block_k, config.load_block_n,
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static_cast<int>(l1_weights.stride(-2)),
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config.swizzle_weights_mode);
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const auto tensor_map_l1_weights_sf = make_tma_sf_desc(cute::UMMA::Major::MN, l1_weights_sf,
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intermediate_hidden * 2, hidden,
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config.block_n, kGranK,
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num_experts_per_rank, 0);
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// NVFP4: L1 output is E2M1 packed, intermediate_hidden/2 bytes per row
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const auto tensor_map_l1_output = make_tma_2d_desc(l2_acts,
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intermediate_hidden / 2, config.num_max_pool_tokens,
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config.block_n / 4, config.store_block_m,
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static_cast<int>(l2_acts.stride(-2)),
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config.swizzle_acts_mode / 4);
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// NVFP4: L2 activations are E2M1 packed, intermediate_hidden/2 bytes per row
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const auto tensor_map_l2_acts = make_tma_2d_desc(l2_acts,
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intermediate_hidden / 2, config.num_max_pool_tokens,
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config.block_k / 2, config.load_block_m,
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static_cast<int>(l2_acts.stride(-2)),
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config.swizzle_acts_mode / 2);
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const auto tensor_map_l2_acts_sf = make_tma_sf_desc(cute::UMMA::Major::MN, l2_acts_sf,
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config.num_padded_sf_pool_tokens, intermediate_hidden,
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config.sf_block_m, kGranK,
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1, 0);
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const auto tensor_map_l2_weights = make_tma_2d_desc(l2_weights,
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intermediate_hidden, num_experts_per_rank * hidden,
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config.block_k, config.load_block_n,
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static_cast<int>(l2_weights.stride(-2)),
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config.swizzle_weights_mode);
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const auto tensor_map_l2_weights_sf = make_tma_sf_desc(cute::UMMA::Major::MN, l2_weights_sf,
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hidden, intermediate_hidden,
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config.block_n, kGranK,
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num_experts_per_rank, 0);
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// Stats can be optional
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int* cumulative_local_expert_recv_stats_ptr = nullptr;
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if (cumulative_local_expert_recv_stats.has_value())
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cumulative_local_expert_recv_stats_ptr = cumulative_local_expert_recv_stats->data_ptr<int>();
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// Launch
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const auto num_sms = device_runtime->get_num_sms();
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const SM100FP8NVFP4MegaMoERuntime::Args args = {
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.num_max_tokens_per_rank = num_max_tokens_per_rank,
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.hidden = hidden, .intermediate_hidden = intermediate_hidden,
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.num_experts = num_experts, .num_topk = num_topk,
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.num_ranks = num_ranks,
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.activation_clamp = activation_clamp,
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.fast_math = fast_math,
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.config = config,
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.y = y.data_ptr(),
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.cumulative_local_expert_recv_stats = cumulative_local_expert_recv_stats_ptr,
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.num_tokens = num_tokens,
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.sym_buffer_ptrs = layout::SymBuffer<>(sym_buffer_ptrs, rank_idx),
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.tensor_map_l1_acts = tensor_map_l1_acts,
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.tensor_map_l1_acts_sf = tensor_map_l1_acts_sf,
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.tensor_map_l1_weights = tensor_map_l1_weights,
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.tensor_map_l1_weights_sf = tensor_map_l1_weights_sf,
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.tensor_map_l1_output = tensor_map_l1_output,
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.tensor_map_l2_acts = tensor_map_l2_acts,
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.tensor_map_l2_acts_sf = tensor_map_l2_acts_sf,
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.tensor_map_l2_weights = tensor_map_l2_weights,
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.tensor_map_l2_weights_sf = tensor_map_l2_weights_sf,
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.launch_args = LaunchArgs(num_sms,
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config.num_dispatch_threads + config.num_non_epilogue_threads + config.num_epilogue_threads,
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config.smem_size, 2)
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};
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const auto code = SM100FP8NVFP4MegaMoERuntime::generate(args);
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const auto runtime = compiler->build("sm100_fp8_nvfp4_mega_moe", code);
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SM100FP8NVFP4MegaMoERuntime::launch(runtime, args);
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}
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} // namespace deep_gemm
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