7f2a703ed5
* Merge with private repo * Update README * Update README * Update README * Add PyTorch requirements * Fix sync scopes for MQA logits (#256) * Update README
362 lines
19 KiB
C++
362 lines
19 KiB
C++
#pragma once
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#include <torch/python.h>
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#include "../../jit/compiler.hpp"
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#include "../../jit/device_runtime.hpp"
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#include "../../jit/kernel_runtime.hpp"
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#include "../../utils/exception.hpp"
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#include "../../utils/format.hpp"
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#include "../heuristics/sm90.hpp"
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#include "epilogue.hpp"
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#include "runtime_utils.hpp"
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namespace deep_gemm {
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class SM90FP8Gemm1D2DRuntime final: public LaunchRuntime<SM90FP8Gemm1D2DRuntime> {
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public:
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struct Args {
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GemmDesc gemm_desc;
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GemmConfig gemm_config;
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LaunchArgs launch_args;
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// TODO: move this into `gemm_desc`
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const std::optional<std::string>& epilogue_type;
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cute::UMMA::Major major_sfb;
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void *sfb, *grouped_layout;
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CUtensorMap tensor_map_a;
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CUtensorMap tensor_map_b;
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CUtensorMap tensor_map_d;
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CUtensorMap tensor_map_sfa;
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};
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static std::string generate_impl(const Args& args) {
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return fmt::format(R"(
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#include <deep_gemm/impls/sm90_fp8_gemm_1d2d.cuh>
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using namespace deep_gemm;
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static void __instantiate_kernel() {{
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auto ptr = reinterpret_cast<void*>(&sm90_fp8_gemm_1d2d_impl<
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{},
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{}, {}, {},
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{},
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{}, {}, {},
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{}, {}, {},
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{},
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{}, {},
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{}, {},
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{}, {},
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{}
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>);
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}};
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)",
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// TODO: add CD dtype
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to_string(args.major_sfb),
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get_compiled_dim(args.gemm_desc.m, 'm', args.gemm_desc.compiled_dims),
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get_compiled_dim(args.gemm_desc.n, 'n', args.gemm_desc.compiled_dims),
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get_compiled_dim(args.gemm_desc.k, 'k', args.gemm_desc.compiled_dims),
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args.gemm_desc.num_groups,
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args.gemm_config.layout.block_m, args.gemm_config.layout.block_n, args.gemm_config.layout.block_k,
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args.gemm_config.storage_config.swizzle_a_mode, args.gemm_config.storage_config.swizzle_b_mode, args.gemm_config.storage_config.swizzle_cd_mode,
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args.gemm_config.pipeline_config.num_stages,
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args.gemm_config.launch_config.num_tma_threads, args.gemm_config.launch_config.num_math_threads,
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args.gemm_config.layout.get_cluster_size(), args.gemm_config.layout.cluster_n > 1,
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args.gemm_config.launch_config.num_sms, to_string(args.gemm_desc.gemm_type),
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get_default_epilogue_type(args.epilogue_type));
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}
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static void launch_impl(const KernelHandle& kernel, const LaunchConfigHandle& config, Args args) {
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// TODO: optimize `args` copy
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DG_CUDA_UNIFIED_CHECK(launch_kernel(kernel, config,
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args.sfb, args.grouped_layout,
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args.gemm_desc.m, args.gemm_desc.n, args.gemm_desc.k,
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args.tensor_map_a, args.tensor_map_b,
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args.tensor_map_d, args.tensor_map_sfa));
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}
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};
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static void sm90_fp8_gemm_1d2d(const torch::Tensor& a, const torch::Tensor& sfa,
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const torch::Tensor& b, const torch::Tensor& sfb,
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const std::optional<torch::Tensor>& c,
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const torch::Tensor& d,
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const int& m, const int& n, const int& k,
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const cute::UMMA::Major& major_a, const cute::UMMA::Major& major_b, const cute::UMMA::Major& major_sfb,
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const std::string& compiled_dims,
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const std::optional<std::string>& epilogue_type = std::nullopt) {
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DG_HOST_ASSERT(not c.has_value() and d.scalar_type() == torch::kBFloat16);
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DG_HOST_ASSERT(major_a == cute::UMMA::Major::K and major_b == cute::UMMA::Major::K);
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const auto desc = GemmDesc {
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.gemm_type = GemmType::Normal,
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.kernel_type = KernelType::Kernel1D2D,
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.m = m, .n = n, .k = k, .num_groups = 1,
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.a_dtype = a.scalar_type(), .b_dtype = b.scalar_type(),
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.cd_dtype = d.scalar_type(),
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.major_a = major_a, .major_b = major_b,
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.with_accumulation = c.has_value(),
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.num_sms = device_runtime->get_num_sms(),
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.tc_util = device_runtime->get_tc_util(), .compiled_dims = compiled_dims
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};
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const auto config = get_best_config<SM90ArchSpec>(desc);
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// Requires no TMA splits
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DG_HOST_ASSERT(config.storage_config.swizzle_a_mode == config.layout.block_k);
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DG_HOST_ASSERT(config.storage_config.swizzle_b_mode == config.layout.block_k);
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const auto tensor_map_a = make_tma_a_desc(major_a, a, m, k,
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config.storage_config.load_block_m,
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config.layout.block_k,
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static_cast<int>(a.stride(get_non_contiguous_dim(major_a))), 1,
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config.storage_config.swizzle_a_mode);
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const auto tensor_map_b = make_tma_b_desc(major_b, b, n, k,
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config.storage_config.load_block_n,
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config.layout.block_k,
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static_cast<int>(b.stride(get_non_contiguous_dim(major_b))), 1,
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config.storage_config.swizzle_b_mode);
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const auto tensor_map_d = make_tma_cd_desc(d, m, static_cast<int>(d.size(-1)),
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config.storage_config.store_block_m,
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config.storage_config.store_block_n,
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static_cast<int>(d.stride(-2)), 1,
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config.storage_config.swizzle_cd_mode);
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const auto tensor_map_sfa = make_tma_sf_desc(cute::UMMA::Major::MN, sfa, m, k,
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config.layout.block_m, config.layout.block_k, 1, 0);
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// Launch
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const SM90FP8Gemm1D2DRuntime::Args& args = {
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.gemm_desc = desc,
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.gemm_config = config,
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.launch_args = LaunchArgs(config.launch_config.num_sms, config.launch_config.num_threads,
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config.pipeline_config.smem_size,
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config.layout.get_cluster_size()),
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.epilogue_type = epilogue_type,
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.major_sfb = major_sfb,
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.sfb = sfb.data_ptr(),
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.grouped_layout = nullptr,
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.tensor_map_a = tensor_map_a,
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.tensor_map_b = tensor_map_b,
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.tensor_map_d = tensor_map_d,
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.tensor_map_sfa = tensor_map_sfa,
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};
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const auto code = SM90FP8Gemm1D2DRuntime::generate(args);
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const auto runtime = compiler->build("sm90_fp8_gemm_1d2d", code);
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SM90FP8Gemm1D2DRuntime::launch(runtime, args);
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}
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static void sm90_m_grouped_fp8_gemm_contiguous_1d2d(const torch::Tensor& a, const torch::Tensor& sfa,
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const torch::Tensor& b, const torch::Tensor& sfb,
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const torch::Tensor& d,
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const torch::Tensor& m_indices,
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const int& num_groups, const int& m, const int& n, const int& k,
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const cute::UMMA::Major& major_a, const cute::UMMA::Major& major_b, const cute::UMMA::Major& major_sfb,
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const std::string& compiled_dims,
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const bool& use_psum_layout,
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const std::optional<int>& expected_m_for_psum_layout) {
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DG_HOST_ASSERT(d.scalar_type() == torch::kBFloat16);
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DG_HOST_ASSERT(major_a == cute::UMMA::Major::K and major_b == cute::UMMA::Major::K);
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const auto gemm_type = use_psum_layout ?
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GemmType::MGroupedContiguousWithPsumLayout : GemmType::MGroupedContiguous;
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// Only psum layout can use expected m
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if (expected_m_for_psum_layout)
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DG_HOST_ASSERT(use_psum_layout);
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const auto desc = GemmDesc {
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.gemm_type = gemm_type,
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.kernel_type = KernelType::Kernel1D2D,
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.m = m, .n = n, .k = k, .num_groups = num_groups,
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.a_dtype = a.scalar_type(), .b_dtype = b.scalar_type(),
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.cd_dtype = d.scalar_type(),
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.major_a = major_a, .major_b = major_b,
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.with_accumulation = false,
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.num_sms = device_runtime->get_num_sms(),
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.tc_util = device_runtime->get_tc_util(), .compiled_dims = compiled_dims,
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.expected_m = expected_m_for_psum_layout.value_or(m),
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.expected_n = n, .expected_k = k,
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.expected_num_groups = expected_m_for_psum_layout.has_value() ? num_groups : 1
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};
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const auto config = get_best_config<SM90ArchSpec>(desc);
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// Requires no TMA splits
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DG_HOST_ASSERT(config.storage_config.swizzle_a_mode == config.layout.block_k);
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DG_HOST_ASSERT(config.storage_config.swizzle_b_mode == config.layout.block_k);
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const auto tensor_map_a = make_tma_a_desc(major_a, a, m, k,
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config.storage_config.load_block_m,
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config.layout.block_k,
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static_cast<int>(a.stride(get_non_contiguous_dim(major_a))), 1,
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config.storage_config.swizzle_a_mode);
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const auto tensor_map_b = make_tma_b_desc(major_b, b, n, k,
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config.storage_config.load_block_n,
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config.layout.block_k,
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static_cast<int>(b.stride(get_non_contiguous_dim(major_b))), num_groups,
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config.storage_config.swizzle_b_mode);
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const auto tensor_map_d = make_tma_cd_desc(d, m, n,
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config.storage_config.store_block_m,
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config.storage_config.store_block_n,
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static_cast<int>(d.stride(-2)), 1,
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config.storage_config.swizzle_cd_mode);
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const auto tensor_map_sfa = make_tma_sf_desc(cute::UMMA::Major::MN, sfa, m, k,
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config.layout.block_m, config.layout.block_k, 1, 0);
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// Launch
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const SM90FP8Gemm1D2DRuntime::Args& args = {
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.gemm_desc = desc,
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.gemm_config = config,
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.launch_args = LaunchArgs(config.launch_config.num_sms, config.launch_config.num_threads,
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config.pipeline_config.smem_size,
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config.layout.get_cluster_size()),
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.epilogue_type = std::nullopt,
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.major_sfb = major_sfb,
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.sfb = sfb.data_ptr(),
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.grouped_layout = m_indices.data_ptr(),
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.tensor_map_a = tensor_map_a,
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.tensor_map_b = tensor_map_b,
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.tensor_map_d = tensor_map_d,
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.tensor_map_sfa = tensor_map_sfa,
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};
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const auto code = SM90FP8Gemm1D2DRuntime::generate(args);
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const auto runtime = compiler->build("sm90_m_grouped_fp8_gemm_contiguous_1d2d", code);
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SM90FP8Gemm1D2DRuntime::launch(runtime, args);
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}
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static void sm90_m_grouped_fp8_gemm_masked_1d2d(const torch::Tensor& a, const torch::Tensor& sfa,
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const torch::Tensor& b, const torch::Tensor& sfb,
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const torch::Tensor& d,
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const torch::Tensor& masked_m,
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const int& num_groups, const int& m, const int& n, const int& k,
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const int& expected_m,
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const cute::UMMA::Major& major_a, const cute::UMMA::Major& major_b, const cute::UMMA::Major& major_sfb,
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const std::string& compiled_dims) {
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DG_HOST_ASSERT(d.scalar_type() == torch::kBFloat16);
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DG_HOST_ASSERT(major_a == cute::UMMA::Major::K and major_b == cute::UMMA::Major::K);
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const auto desc = GemmDesc {
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.gemm_type = GemmType::MGroupedMasked,
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.kernel_type = KernelType::Kernel1D2D,
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.m = m, .n = n, .k = k, .num_groups = num_groups,
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.a_dtype = a.scalar_type(), .b_dtype = b.scalar_type(),
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.cd_dtype = d.scalar_type(),
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.major_a = major_a, .major_b = major_b,
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.with_accumulation = false,
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.num_sms = device_runtime->get_num_sms(),
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.tc_util = device_runtime->get_tc_util(), .compiled_dims = compiled_dims,
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.expected_m = expected_m, .expected_n = n, .expected_k = k, .expected_num_groups = num_groups
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};
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const auto config = get_best_config<SM90ArchSpec>(desc);
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// Requires no TMA splits
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DG_HOST_ASSERT(config.storage_config.swizzle_a_mode == config.layout.block_k);
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DG_HOST_ASSERT(config.storage_config.swizzle_b_mode == config.layout.block_k);
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const auto tensor_map_a = make_tma_a_desc(major_a, a, m, k,
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config.storage_config.load_block_m,
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config.layout.block_k,
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static_cast<int>(a.stride(get_non_contiguous_dim(major_a))), num_groups,
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config.storage_config.swizzle_a_mode);
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const auto tensor_map_b = make_tma_b_desc(major_b, b, n, k,
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config.storage_config.load_block_n,
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config.layout.block_k,
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static_cast<int>(b.stride(get_non_contiguous_dim(major_b))), num_groups,
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config.storage_config.swizzle_b_mode);
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const auto tensor_map_d = make_tma_cd_desc(d, m, n,
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config.storage_config.store_block_m,
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config.storage_config.store_block_n,
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static_cast<int>(d.stride(-2)), num_groups,
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config.storage_config.swizzle_cd_mode);
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const auto tensor_map_sfa = make_tma_sf_desc(cute::UMMA::Major::MN, sfa, m, k,
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config.layout.block_m, config.layout.block_k, num_groups, 0);
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// Launch
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const SM90FP8Gemm1D2DRuntime::Args& args = {
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.gemm_desc = desc,
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.gemm_config = config,
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.launch_args = LaunchArgs(config.launch_config.num_sms, config.launch_config.num_threads,
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config.pipeline_config.smem_size,
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config.layout.get_cluster_size()),
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.epilogue_type = std::nullopt,
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.major_sfb = major_sfb,
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.sfb = sfb.data_ptr(),
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.grouped_layout = masked_m.data_ptr(),
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.tensor_map_a = tensor_map_a,
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.tensor_map_b = tensor_map_b,
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.tensor_map_d = tensor_map_d,
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.tensor_map_sfa = tensor_map_sfa,
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};
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const auto code = SM90FP8Gemm1D2DRuntime::generate(args);
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const auto runtime = compiler->build("sm90_fp8_m_grouped_gemm_masked_1d2d", code);
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SM90FP8Gemm1D2DRuntime::launch(runtime, args);
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}
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static void sm90_fp8_bmm(const torch::Tensor& a, const torch::Tensor& sfa,
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const torch::Tensor& b, const torch::Tensor& sfb,
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const std::optional<torch::Tensor>& c,
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const torch::Tensor& d,
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const int& batch_size, const int& m, const int& n, const int& k,
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const cute::UMMA::Major& major_a, const cute::UMMA::Major& major_b, const cute::UMMA::Major& major_sfb,
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const std::string& compiled_dims) {
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DG_HOST_ASSERT(d.scalar_type() == torch::kBFloat16);
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DG_HOST_ASSERT(major_a == cute::UMMA::Major::K and major_b == cute::UMMA::Major::K);
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const auto desc = GemmDesc {
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.gemm_type = GemmType::Batched,
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.kernel_type = KernelType::Kernel1D2D,
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.m = m, .n = n, .k = k, .num_groups = batch_size,
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.a_dtype = a.scalar_type(), .b_dtype = b.scalar_type(),
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.cd_dtype = d.scalar_type(),
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.major_a = major_a, .major_b = major_b,
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.with_accumulation = c.has_value(),
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.num_sms = device_runtime->get_num_sms(),
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.tc_util = device_runtime->get_tc_util(), .compiled_dims = compiled_dims
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};
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const auto config = get_best_config<SM90ArchSpec>(desc);
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// Requires no TMA splits
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DG_HOST_ASSERT(config.storage_config.swizzle_a_mode == config.layout.block_k);
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DG_HOST_ASSERT(config.storage_config.swizzle_b_mode == config.layout.block_k);
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const int load_block_m = config.storage_config.load_block_m;
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const auto tensor_map_a = make_tma_3d_desc(a, k, m, batch_size,
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config.layout.block_k, load_block_m, 1,
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a.stride(1),
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a.stride(0),
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config.storage_config.swizzle_a_mode);
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const int load_block_n = config.storage_config.load_block_n;
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const auto tensor_map_b = make_tma_3d_desc(b, k, n, batch_size,
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config.layout.block_k, load_block_n, 1,
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b.stride(1),
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b.stride(0),
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config.storage_config.swizzle_b_mode);
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const int store_block_m = config.storage_config.store_block_m;
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const int store_block_n = config.storage_config.store_block_n;
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const auto tensor_map_d = make_tma_3d_desc(d, n, m, batch_size,
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store_block_n, store_block_m, 1,
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d.stride(1), d.stride(0),
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config.storage_config.swizzle_cd_mode);
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const auto tensor_map_sfa = make_tma_sf_desc(cute::UMMA::Major::MN, sfa, m, k,
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config.layout.block_m, config.layout.block_k, batch_size, 0);
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// Launch
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const SM90FP8Gemm1D2DRuntime::Args& args = {
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.gemm_desc = desc,
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.gemm_config = config,
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.launch_args = LaunchArgs(config.launch_config.num_sms, config.launch_config.num_threads,
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config.pipeline_config.smem_size,
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config.layout.get_cluster_size()),
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.epilogue_type = std::nullopt,
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.major_sfb = major_sfb,
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.sfb = sfb.data_ptr(),
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.grouped_layout = nullptr,
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.tensor_map_a = tensor_map_a,
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.tensor_map_b = tensor_map_b,
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.tensor_map_d = tensor_map_d,
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.tensor_map_sfa = tensor_map_sfa,
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};
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const auto code = SM90FP8Gemm1D2DRuntime::generate(args);
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const auto runtime = compiler->build("sm90_fp8_gemm_1d2d", code);
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SM90FP8Gemm1D2DRuntime::launch(runtime, args);
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}
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} // namespace deep_gemm
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