7f2a703ed5
* Merge with private repo * Update README * Update README * Update README * Add PyTorch requirements * Fix sync scopes for MQA logits (#256) * Update README
230 lines
11 KiB
C++
230 lines
11 KiB
C++
#pragma once
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#include <torch/python.h>
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#include "../../jit/compiler.hpp"
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#include "../../jit/device_runtime.hpp"
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#include "../../jit/kernel_runtime.hpp"
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#include "../../utils/exception.hpp"
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#include "../../utils/format.hpp"
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#include "../heuristics/sm90.hpp"
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#include "runtime_utils.hpp"
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namespace deep_gemm {
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class SM90FP8Gemm1D1DRuntime final: public LaunchRuntime<SM90FP8Gemm1D1DRuntime> {
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public:
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struct Args {
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GemmDesc gemm_desc;
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GemmConfig gemm_config;
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LaunchArgs launch_args;
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void *gmem_a_ptr;
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void *gmem_b_ptr;
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void *grouped_layout;
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void *tensor_map_buffer;
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CUtensorMap tensor_map_a_base;
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CUtensorMap tensor_map_b_base;
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CUtensorMap tensor_map_sfa;
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CUtensorMap tensor_map_sfb;
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CUtensorMap tensor_map_cd;
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};
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static std::string generate_impl(const Args& args) {
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return fmt::format(R"(
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#include <deep_gemm/impls/sm90_fp8_gemm_1d1d.cuh>
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using namespace deep_gemm;
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static void __instantiate_kernel() {{
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auto ptr = reinterpret_cast<void*>(&sm90_fp8_gemm_1d1d_impl<
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{}, {}, {},
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{},
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{}, {}, {},
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{}, {},
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{},
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{}, {},
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{}, {},
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{},
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{}, {}
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>);
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}};
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)",
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get_compiled_dim(args.gemm_desc.m, 'm', args.gemm_desc.compiled_dims),
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get_compiled_dim(args.gemm_desc.n, 'n', args.gemm_desc.compiled_dims),
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get_compiled_dim(args.gemm_desc.k, 'k', args.gemm_desc.compiled_dims),
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args.gemm_desc.num_groups,
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args.gemm_config.layout.block_m, args.gemm_config.layout.block_n, args.gemm_config.layout.block_k,
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args.gemm_config.storage_config.swizzle_a_mode, args.gemm_config.storage_config.swizzle_b_mode,
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args.gemm_config.pipeline_config.num_stages,
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args.gemm_config.launch_config.num_tma_threads, args.gemm_config.launch_config.num_math_threads,
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args.gemm_config.layout.get_cluster_size(), args.gemm_config.layout.cluster_n > 1,
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args.gemm_config.launch_config.num_sms, to_string(args.gemm_desc.gemm_type),
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to_string(args.gemm_desc.cd_dtype));
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}
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static void launch_impl(const KernelHandle& kernel, const LaunchConfigHandle& config, Args args) {
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DG_CUDA_UNIFIED_CHECK(launch_kernel(kernel, config,
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args.gmem_a_ptr, args.gmem_b_ptr,
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args.grouped_layout,
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args.tensor_map_buffer,
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args.gemm_desc.m, args.gemm_desc.n, args.gemm_desc.k,
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args.tensor_map_a_base, args.tensor_map_b_base,
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args.tensor_map_sfa, args.tensor_map_sfb,
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args.tensor_map_cd));
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}
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};
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static void sm90_fp8_gemm_1d1d(const torch::Tensor& a, const torch::Tensor& sfa,
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const torch::Tensor& b, const torch::Tensor& sfb,
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const std::optional<torch::Tensor>& c,
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const torch::Tensor& d,
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const int& m, const int& n, const int& k,
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const cute::UMMA::Major& major_a, const cute::UMMA::Major& major_b,
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const std::string& compiled_dims) {
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DG_HOST_ASSERT(c.has_value() and d.scalar_type() == torch::kFloat);
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DG_HOST_ASSERT(major_a == cute::UMMA::Major::K and major_b == cute::UMMA::Major::K);
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const auto desc = GemmDesc {
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.gemm_type = GemmType::Normal,
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.kernel_type = KernelType::Kernel1D1D,
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.m = m, .n = n, .k = k, .num_groups = 1,
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.a_dtype = a.scalar_type(), .b_dtype = b.scalar_type(),
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.cd_dtype = d.scalar_type(),
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.major_a = major_a, .major_b = major_b,
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.with_accumulation = c.has_value(),
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.num_sms = device_runtime->get_num_sms(),
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.tc_util = device_runtime->get_tc_util(), .compiled_dims = compiled_dims
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};
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const auto config = get_best_config<SM90ArchSpec>(desc);
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// Requires no TMA splits
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DG_HOST_ASSERT(config.storage_config.swizzle_a_mode == config.layout.block_k);
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DG_HOST_ASSERT(config.storage_config.swizzle_b_mode == config.layout.block_k);
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const auto tensor_map_a = make_tma_a_desc(major_a, a, m, k,
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config.storage_config.load_block_m,
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config.layout.block_k, k, 1,
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config.storage_config.swizzle_a_mode);
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const auto tensor_map_b = make_tma_b_desc(major_b, b, n, k,
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config.storage_config.load_block_n,
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config.layout.block_k, k, 1,
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config.storage_config.swizzle_b_mode);
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const auto tensor_map_sfa = make_tma_sf_desc(cute::UMMA::Major::MN, sfa, m, k,
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config.layout.block_m, config.layout.block_k, 1, 0);
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const auto tensor_map_sfb = make_tma_sf_desc(cute::UMMA::Major::MN, sfb, n, k,
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config.layout.block_n, config.layout.block_k, 1, 0);
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const auto tensor_map_cd = make_tma_cd_desc(d, m, n,
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config.storage_config.store_block_m,
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config.storage_config.store_block_n,
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static_cast<int>(d.stride(-2)), 1,
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0);
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// Launch
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const SM90FP8Gemm1D1DRuntime::Args& args = {
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.gemm_desc = desc,
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.gemm_config = config,
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.launch_args = LaunchArgs(config.launch_config.num_sms, config.launch_config.num_threads,
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config.pipeline_config.smem_size,
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config.layout.get_cluster_size()),
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.gmem_a_ptr = nullptr,
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.gmem_b_ptr = nullptr,
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.grouped_layout = nullptr,
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.tensor_map_buffer = nullptr,
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.tensor_map_a_base = tensor_map_a,
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.tensor_map_b_base = tensor_map_b,
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.tensor_map_sfa = tensor_map_sfa,
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.tensor_map_sfb = tensor_map_sfb,
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.tensor_map_cd = tensor_map_cd,
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};
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const auto code = SM90FP8Gemm1D1DRuntime::generate(args);
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const auto runtime = compiler->build("sm90_fp8_gemm_1d1d", code);
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SM90FP8Gemm1D1DRuntime::launch(runtime, args);
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}
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static void sm90_k_grouped_fp8_gemm_1d1d(const torch::Tensor& a, const torch::Tensor& sfa,
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const torch::Tensor& b, const torch::Tensor& sfb,
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const std::optional<torch::Tensor>& c,
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const torch::Tensor& d,
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const int& m, const int& n,
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const std::vector<int>& ks, const torch::Tensor& ks_tensor,
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const torch::Tensor& tensor_map_buffer,
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const cute::UMMA::Major& major_a, const cute::UMMA::Major& major_b,
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const std::string& compiled_dims) {
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DG_HOST_ASSERT(c.has_value() and d.scalar_type() == torch::kFloat);
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DG_HOST_ASSERT(major_a == cute::UMMA::Major::K and major_b == cute::UMMA::Major::K);
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// TODO: refactor with the mk alignment function
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const auto num_groups = static_cast<int>(ks.size());
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int first_k = 0, sum_k = 0, sum_sf_k = 0, max_k = 0;
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for (int i = 0; i < num_groups; ++ i) {
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if (first_k == 0 and ks[i] != 0)
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first_k = ks[i];
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sum_k += ks[i], sum_sf_k += ceil_div(ks[i], 128);
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max_k = std::max(max_k, ks[i]);
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DG_HOST_ASSERT(ks[i] % 128 == 0);
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}
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// Get config using max K for better performance
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const auto desc = GemmDesc {
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.gemm_type = GemmType::KGroupedContiguous,
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.kernel_type = KernelType::Kernel1D1D,
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.m = m, .n = n, .k = sum_k, .num_groups = num_groups,
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.a_dtype = a.scalar_type(), .b_dtype = b.scalar_type(),
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.cd_dtype = d.scalar_type(),
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.major_a = major_a, .major_b = major_b,
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.with_accumulation = c.has_value(),
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.num_sms = device_runtime->get_num_sms(),
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.tc_util = device_runtime->get_tc_util(), .compiled_dims = compiled_dims,
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.expected_m = m, .expected_n = n, .expected_k = max_k, .expected_num_groups = num_groups
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};
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const auto config = get_best_config<SM90ArchSpec>(desc);
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// Requires no TMA splits
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DG_HOST_ASSERT(config.storage_config.swizzle_a_mode == config.layout.block_k);
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DG_HOST_ASSERT(config.storage_config.swizzle_b_mode == config.layout.block_k);
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const auto tensor_map_a_base = make_tma_a_desc(major_a, a, m, first_k,
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config.storage_config.load_block_m,
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config.layout.block_k, first_k, 1,
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config.storage_config.swizzle_a_mode);
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const auto tensor_map_b_base = make_tma_b_desc(major_b, b, n, first_k,
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config.storage_config.load_block_n,
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config.layout.block_k, first_k, 1,
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config.storage_config.swizzle_b_mode);
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const auto tensor_map_sfa = make_tma_sf_desc(cute::UMMA::Major::MN, sfa, m, sum_sf_k * 128,
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config.layout.block_m, config.layout.block_k, 1, 0);
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const auto tensor_map_sfb = make_tma_sf_desc(cute::UMMA::Major::MN, sfb, n, sum_sf_k * 128,
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config.layout.block_n, config.layout.block_k, 1, 0);
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const auto tensor_map_cd = make_tma_cd_desc(d, m, n,
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config.storage_config.store_block_m,
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config.storage_config.store_block_n,
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static_cast<int>(d.stride(-2)), num_groups,
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config.storage_config.swizzle_cd_mode);
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// Launch
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const SM90FP8Gemm1D1DRuntime::Args& args = {
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.gemm_desc = desc,
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.gemm_config = config,
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.launch_args = LaunchArgs(config.launch_config.num_sms, config.launch_config.num_threads,
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config.pipeline_config.smem_size,
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config.layout.get_cluster_size()),
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.gmem_a_ptr = a.data_ptr(),
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.gmem_b_ptr = b.data_ptr(),
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.grouped_layout = ks_tensor.data_ptr(),
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.tensor_map_buffer = tensor_map_buffer.data_ptr(),
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.tensor_map_a_base = tensor_map_a_base,
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.tensor_map_b_base = tensor_map_b_base,
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.tensor_map_sfa = tensor_map_sfa,
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.tensor_map_sfb = tensor_map_sfb,
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.tensor_map_cd = tensor_map_cd,
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};
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const auto code = SM90FP8Gemm1D1DRuntime::generate(args);
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const auto runtime = compiler->build("sm90_fp8_gemm_1d1d", code);
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SM90FP8Gemm1D1DRuntime::launch(runtime, args);
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}
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} // namespace deep_gemm
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