Multiple updates and refactorings (#280)
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@@ -37,11 +37,12 @@ static std::string to_string(const cute::UMMA::Major& major) {
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static std::string to_string(const GemmType& type) {
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switch (type) {
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case GemmType::Normal: return "GemmType::Normal";
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case GemmType::MGroupedContiguous: return "GemmType::MGroupedContiguous";
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case GemmType::MGroupedMasked: return "GemmType::MGroupedMasked";
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case GemmType::KGroupedContiguous: return "GemmType::KGroupedContiguous";
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case GemmType::Batched: return "GemmType::Batched";
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case GemmType::Normal: return "GemmType::Normal";
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case GemmType::MGroupedContiguous: return "GemmType::MGroupedContiguous";
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case GemmType::MGroupedMasked: return "GemmType::MGroupedMasked";
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case GemmType::MGroupedContiguousWithPsumLayout: return "GemmType::MGroupedContiguousWithPsumLayout";
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case GemmType::KGroupedContiguous: return "GemmType::KGroupedContiguous";
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case GemmType::Batched: return "GemmType::Batched";
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}
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DG_HOST_UNREACHABLE("Unknown GEMM type");
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}
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@@ -51,6 +52,8 @@ static std::string to_string(const at::ScalarType& dtype) {
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case torch::kInt: return "int";
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case torch::kFloat: return "float";
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case torch::kBFloat16: return "cutlass::bfloat16_t";
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case torch::kFloat8_e4m3fn: return "cutlass::float_e4m3_t";
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case kPackedFP4: return "cutlass::detail::float_e2m1_unpacksmem_t";
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default: DG_HOST_UNREACHABLE("Unsupported dtype");
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}
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}
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@@ -65,6 +68,7 @@ static CUtensorMapDataType aten_dtype_to_tensor_map_dtype(const at::ScalarType&
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case torch::kFloat: return CU_TENSOR_MAP_DATA_TYPE_FLOAT32;
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case torch::kBFloat16: return CU_TENSOR_MAP_DATA_TYPE_BFLOAT16;
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case torch::kFloat8_e4m3fn: return CU_TENSOR_MAP_DATA_TYPE_UINT8;
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case kPackedFP4: return CU_TENSOR_MAP_DATA_TYPE_16U4_ALIGN16B;
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default: DG_HOST_UNREACHABLE("Unsupported dtype");
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}
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}
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@@ -98,6 +102,10 @@ static CUtensorMap make_tma_2d_desc(const torch::Tensor& t,
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if (swizzle_mode != 0)
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smem_inner_dim = swizzle_mode / elem_size;
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// Inner dim must be a multiple of 64B for .b4x16_p64
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if (t.scalar_type() == kPackedFP4)
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DG_HOST_ASSERT(gmem_inner_dim % 128 == 0);
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CUtensorMap tensor_map;
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const cuuint64_t gmem_dims[2] = {static_cast<cuuint64_t>(gmem_inner_dim), static_cast<cuuint64_t>(gmem_outer_dim)};
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const cuuint32_t smem_dims[2] = {static_cast<cuuint32_t>(smem_inner_dim), static_cast<cuuint32_t>(smem_outer_dim)};
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@@ -126,6 +134,10 @@ static CUtensorMap make_tma_3d_desc(const torch::Tensor& t,
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if (swizzle_mode != 0)
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smem_dim_0 = swizzle_mode / elem_size;
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// Inner dim must be a multiple of 64B for .b4x16_p64
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if (t.scalar_type() == kPackedFP4)
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DG_HOST_ASSERT(gmem_dim_0 % 128 == 0);
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CUtensorMap tensor_map;
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const cuuint64_t gmem_dims[3] = {static_cast<cuuint64_t>(gmem_dim_0), static_cast<cuuint64_t>(gmem_dim_1), static_cast<cuuint64_t>(gmem_dim_2),};
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const cuuint32_t smem_dims[3] = {static_cast<cuuint32_t>(smem_dim_0), static_cast<cuuint32_t>(smem_dim_1), static_cast<cuuint32_t>(smem_dim_2)};
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@@ -204,7 +216,7 @@ static CUtensorMap make_tma_cd_desc(const torch::Tensor& t,
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static CUtensorMap make_tma_sf_desc(const cute::UMMA::Major& major,
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const torch::Tensor& t,
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int shape_mn, int shape_k,
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const int& block_mn, const int& block_k,
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const int& block_mn, const int& gran_k,
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const int& num_groups,
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const int& swizzle_mode, const int& swizzle_base = 0,
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const bool& allow_tf32 = false) {
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@@ -215,7 +227,7 @@ static CUtensorMap make_tma_sf_desc(const cute::UMMA::Major& major,
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shape_mn = get_tma_aligned_size(shape_mn, static_cast<int>(t.element_size()));
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return make_tma_2d_desc(t,
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shape_mn, ceil_div(shape_k, block_k * (t.scalar_type() == torch::kFloat ? 1 : 4)) * num_groups,
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shape_mn, ceil_div(shape_k, gran_k * (t.scalar_type() == torch::kFloat ? 1 : 4)) * num_groups,
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block_mn, 1,
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shape_mn,
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swizzle_mode, swizzle_base,
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